mirror of https://github.com/YosysHQ/yosys.git
18 lines
464 B
Plaintext
18 lines
464 B
Plaintext
|
read_verilog memory.v
|
||
|
|
hierarchy -top top
|
||
|
|
proc
|
||
|
|
memory -nomap
|
||
|
|
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
|
||
|
|
memory
|
||
|
|
opt -full
|
||
|
|
|
||
|
|
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||
|
|
sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
|
||
|
|
|
||
|
|
design -load postopt
|
||
|
|
cd top
|
||
|
|
select -assert-count 1 t:BUFG
|
||
|
|
select -assert-count 8 t:FDRE
|
||
|
|
select -assert-count 8 t:RAM64X1D
|
||
|
|
select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
|