yosys/tests/verilog/func_tern_hint.ys

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read_verilog -sv func_tern_hint.sv
proc
opt
sat -verify -seq 1 -prove-asserts -show-all
verilog: fix width/sign detection for functions 2022-05-30 15:45:39 -05:00			`read_verilog -sv func_tern_hint.sv`
			`proc`
			`opt`
			`sat -verify -seq 1 -prove-asserts -show-all`