mirror of https://github.com/YosysHQ/yosys.git
14 lines
279 B
Plaintext
14 lines
279 B
Plaintext
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read_verilog ../common/blockram.v
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hierarchy -top sync_ram_sp
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proc
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memory -nomap
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equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
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memory
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opt -full
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design -load postopt
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cd sync_ram_sp
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select -assert-count 1 t:EG_PHY_BRAM
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select -assert-none t:EG_PHY_BRAM %% t:* %D
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