mirror of https://github.com/YosysHQ/yosys.git
41 lines
726 B
Plaintext
41 lines
726 B
Plaintext
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read_verilog <<EOT
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`define N 256
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module top(input [`N-1:0] a, output o);
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wire [`N-2:0] w;
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assign w[0] = a[0] & a[1];
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genvar i;
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generate for (i = 1; i < `N-1; i++)
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assign w[i] = w[i-1] & a[i+1];
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endgenerate
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assign o = w[`N-2];
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endmodule
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EOT
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simplemap
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dump
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design -save gold
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abc9 -lut 4
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design -load gold
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abc9 -lut 4 -fast
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design -load gold
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scratchpad -copy abc9.script.default.area abc9.script
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abc9 -lut 4
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design -load gold
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scratchpad -copy abc9.script.default.fast abc9.script
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abc9 -lut 4
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design -load gold
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scratchpad -copy abc9.script.flow abc9.script
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abc9 -lut 4
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design -load gold
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scratchpad -copy abc9.script.flow2 abc9.script
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abc9 -lut 4
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design -load gold
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scratchpad -copy abc9.script.flow3 abc9.script
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abc9 -lut 4
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