mirror of https://github.com/YosysHQ/yosys.git
16 lines
308 B
Verilog
16 lines
308 B
Verilog
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module test(clk, s, a, y);
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input clk, s;
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input [15:0] a;
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output [15:0] y;
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reg [15:0] b, c;
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always @(posedge clk) begin
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b <= a;
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c <= b;
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end
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wire [15:0] state_a = (a ^ b) + c;
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wire [15:0] state_b = (a ^ b) - c;
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assign y = !s ? state_a : state_b;
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endmodule
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