mirror of https://github.com/YosysHQ/yosys.git
9 lines
290 B
Verilog
9 lines
290 B
Verilog
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module \$__FABULOUS_IBUF (input PAD, output O);
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IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .O(O), .T(1'b1));
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endmodule
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module \$__FABULOUS_OBUF (output PAD, input I);
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IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .I(I), .T(1'b0));
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endmodule
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