mirror of https://github.com/YosysHQ/yosys.git
14 lines
272 B
Verilog
14 lines
272 B
Verilog
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`default_nettype none
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module latch_002
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(dword, sel, st, vect);
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output reg [63:0] dword;
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input wire [7:0] vect;
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input wire [7:0] sel;
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input wire st;
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always @(*) begin
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if (st)
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dword[8*sel +:8] <= vect[7:0];
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end
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endmodule // latch_002
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