mirror of https://github.com/YosysHQ/yosys.git
45 lines
914 B
Plaintext
45 lines
914 B
Plaintext
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read_verilog -sv meminit.v
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chparam -set DEPTH_LOG2 5 -set WIDTH 36
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prep
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opt_dff
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prep -rdff
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synth_nanoxplore
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clean_zerowidth
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select -assert-none t:$mem_v2 t:$mem
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read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
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prep
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async2sync
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hierarchy -top top
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sim -assert -q -n 66 -clock clk
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design -reset
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read_verilog -sv meminit.v
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chparam -set DEPTH_LOG2 6 -set WIDTH 18
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prep
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opt_dff
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prep -rdff
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synth_nanoxplore
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clean_zerowidth
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select -assert-none t:$mem_v2 t:$mem
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read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
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prep
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async2sync
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hierarchy -top top
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sim -assert -q -n 34 -clock clk
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design -reset
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read_verilog -sv meminit.v
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chparam -set DEPTH_LOG2 8 -set WIDTH 18
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prep
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opt_dff
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prep -rdff
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synth_nanoxplore
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clean_zerowidth
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select -assert-none t:$mem_v2 t:$mem
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read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
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prep
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async2sync
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hierarchy -top top
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sim -assert -q -n 258 -clock clk
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