yosys/frontends/ast/Makefile.inc


OBJS += frontends/ast/ast.o
OBJS += frontends/ast/simplify.o
OBJS += frontends/ast/genrtlil.o
OBJS += frontends/ast/dpicall.o
OBJS += frontends/ast/ast_binding.o
initial import 2013-01-05 04:13:26 -06:00
			`OBJS += frontends/ast/ast.o`
			`OBJS += frontends/ast/simplify.o`
			`OBJS += frontends/ast/genrtlil.o`
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 05:43:51 -05:00			`OBJS += frontends/ast/dpicall.o`
Generate an RTLIL representation of bind constructs This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class. 2020-04-20 10:06:53 -05:00			`OBJS += frontends/ast/ast_binding.o`
initial import 2013-01-05 04:13:26 -06:00