mirror of https://github.com/YosysHQ/yosys.git
54 lines
2.9 KiB
Plaintext
54 lines
2.9 KiB
Plaintext
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set hdlin_ignore_full_case false
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set hdlin_warn_on_mismatch_message "FMR_ELAB-115 FMR_VLOG-079 FMR_VLOG-091"
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read_verilog -container r -libname WORK -01 rtl/or1200_alu.v
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read_verilog -container r -libname WORK -01 rtl/or1200_amultp2_32x32.v
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read_verilog -container r -libname WORK -01 rtl/or1200_cfgr.v
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read_verilog -container r -libname WORK -01 rtl/or1200_cpu.v
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read_verilog -container r -libname WORK -01 rtl/or1200_ctrl.v
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read_verilog -container r -libname WORK -01 rtl/or1200_dc_fsm.v
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read_verilog -container r -libname WORK -01 rtl/or1200_dc_ram.v
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read_verilog -container r -libname WORK -01 rtl/or1200_dc_tag.v
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read_verilog -container r -libname WORK -01 rtl/or1200_dc_top.v
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read_verilog -container r -libname WORK -01 rtl/or1200_dmmu_tlb.v
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read_verilog -container r -libname WORK -01 rtl/or1200_dmmu_top.v
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read_verilog -container r -libname WORK -01 rtl/or1200_dpram.v
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read_verilog -container r -libname WORK -01 rtl/or1200_du.v
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read_verilog -container r -libname WORK -01 rtl/or1200_except.v
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read_verilog -container r -libname WORK -01 rtl/or1200_fpu.v
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read_verilog -container r -libname WORK -01 rtl/or1200_freeze.v
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read_verilog -container r -libname WORK -01 rtl/or1200_genpc.v
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read_verilog -container r -libname WORK -01 rtl/or1200_ic_fsm.v
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read_verilog -container r -libname WORK -01 rtl/or1200_ic_ram.v
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read_verilog -container r -libname WORK -01 rtl/or1200_ic_tag.v
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read_verilog -container r -libname WORK -01 rtl/or1200_ic_top.v
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read_verilog -container r -libname WORK -01 rtl/or1200_if.v
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read_verilog -container r -libname WORK -01 rtl/or1200_immu_tlb.v
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read_verilog -container r -libname WORK -01 rtl/or1200_immu_top.v
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read_verilog -container r -libname WORK -01 rtl/or1200_lsu.v
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read_verilog -container r -libname WORK -01 rtl/or1200_mem2reg.v
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read_verilog -container r -libname WORK -01 rtl/or1200_mult_mac.v
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read_verilog -container r -libname WORK -01 rtl/or1200_operandmuxes.v
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read_verilog -container r -libname WORK -01 rtl/or1200_pic.v
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read_verilog -container r -libname WORK -01 rtl/or1200_pm.v
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read_verilog -container r -libname WORK -01 rtl/or1200_qmem_top.v
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read_verilog -container r -libname WORK -01 rtl/or1200_reg2mem.v
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read_verilog -container r -libname WORK -01 rtl/or1200_rf.v
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read_verilog -container r -libname WORK -01 rtl/or1200_sb.v
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read_verilog -container r -libname WORK -01 rtl/or1200_spram_32_bw.v
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read_verilog -container r -libname WORK -01 rtl/or1200_spram.v
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read_verilog -container r -libname WORK -01 rtl/or1200_sprs.v
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read_verilog -container r -libname WORK -01 rtl/or1200_top.v
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read_verilog -container r -libname WORK -01 rtl/or1200_tt.v
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read_verilog -container r -libname WORK -01 rtl/or1200_wb_biu.v
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read_verilog -container r -libname WORK -01 rtl/or1200_wbmux.v
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set_top r:/WORK/or1200_top
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read_verilog -container i -libname WORK -01 synth.v
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read_verilog -container i -technology_library -libname TECH_WORK -01 ../../techlibs/stdcells_sim.v
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set_top i:/WORK/or1200_top
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if ![verify] start_gui exit
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