2019-08-13 14:36:59 -05:00
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#!/usr/bin/env python3
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from argparse import ArgumentParser
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from io import StringIO
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from enum import Enum, auto
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import os.path
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import sys
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2019-08-28 10:28:01 -05:00
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import re
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2019-08-13 14:36:59 -05:00
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class Cell:
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def __init__(self, name, keep=False, port_attrs={}):
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self.name = name
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self.keep = keep
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self.port_attrs = port_attrs
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synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
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CELLS = [
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# Design element types listed in:
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# - UG607 (Spartan 3)
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# - UG613 (Spartan 3A)
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# - UG617 (Spartan 3E)
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# - UG615 (Spartan 6)
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# - UG619 (Virtex 4)
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# - UG621 (Virtex 5)
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# - UG623 (Virtex 6)
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# - UG953 (Series 7)
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# - UG974 (Ultrascale)
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# CLB -- RAM/ROM.
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2019-12-03 23:31:09 -06:00
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# Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('ROM16X1'),
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# Cell('ROM32X1'),
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# Cell('ROM64X1'),
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# Cell('ROM128X1'),
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# Cell('ROM256X1'),
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synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
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# CLB -- registers/latches.
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# Virtex 1/2/4/5, Spartan 3.
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2019-11-27 11:13:00 -06:00
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# Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}),
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2019-12-18 06:42:26 -06:00
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# Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}),
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2019-11-27 11:13:00 -06:00
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# Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}),
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synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
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# Virtex 6, Spartan 6, Series 7, Ultrascale.
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# Cell('FDCE'),
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# Cell('FDPE'),
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# Cell('FDRE'),
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# Cell('FDSE'),
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# Cell('LDCE'),
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# Cell('LDPE'),
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2019-11-27 11:13:00 -06:00
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# Cell('AND2B1L'),
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# Cell('OR2L'),
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synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
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# CLB -- other.
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2019-09-14 19:49:53 -05:00
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# Cell('LUT1'),
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# Cell('LUT2'),
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# Cell('LUT3'),
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# Cell('LUT4'),
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# Cell('LUT5'),
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# Cell('LUT6'),
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synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
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# Cell('LUT6_2'),
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2019-11-27 11:13:00 -06:00
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# Cell('MUXF5'),
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# Cell('MUXF6'),
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2019-09-14 19:49:53 -05:00
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# Cell('MUXF7'),
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# Cell('MUXF8'),
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2019-11-27 11:13:00 -06:00
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# Cell('MUXF9'),
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synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
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# Cell('CARRY4'),
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2019-11-27 11:13:00 -06:00
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# Cell('CARRY8'),
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synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
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# Cell('MUXCY'),
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# Cell('XORCY'),
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2019-11-27 11:13:00 -06:00
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# Cell('ORCY'),
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# Cell('MULT_AND'),
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# Cell('SRL16', port_attrs={'CLK': ['clkbuf_sink']}),
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2019-09-14 19:49:53 -05:00
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# Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
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2019-11-27 11:13:00 -06:00
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# Cell('SRLC16', port_attrs={'CLK': ['clkbuf_sink']}),
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synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
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# Cell('SRLC16E', port_attrs={'CLK': ['clkbuf_sink']}),
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2019-09-14 19:49:53 -05:00
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# Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
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2019-11-27 11:13:00 -06:00
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# Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
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2019-09-14 19:49:53 -05:00
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synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
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# Block RAM.
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# Virtex.
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# TODO: RAMB4_*
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# Virtex 2, Spartan 3.
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Cell('RAMB16_S1', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('RAMB16_S2', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('RAMB16_S4', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('RAMB16_S9', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('RAMB16_S18', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('RAMB16_S36', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('RAMB16_S1_S1', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S1_S2', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S1_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S1_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S1_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S1_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S2_S2', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S2_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S2_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S2_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S2_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S4_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S4_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S4_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S4_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S9_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S9_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S9_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S18_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S18_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16_S36_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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# Spartan 3A (in addition to above).
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Cell('RAMB16BWE_S18', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('RAMB16BWE_S36', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('RAMB16BWE_S18_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16BWE_S18_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16BWE_S36_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16BWE_S36_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('RAMB16BWE_S36_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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# Spartan 3A DSP.
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2020-02-14 14:54:47 -06:00
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Cell('RAMB16BWER', port_attrs={ 'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
# Spartan 6 (in addition to above).
|
2020-02-14 14:54:47 -06:00
|
|
|
Cell('RAMB8BWER', port_attrs={ 'CLKAWRCLK': ['clkbuf_sink'], 'CLKBRDCLK': ['clkbuf_sink']}),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
# Virtex 4.
|
|
|
|
Cell('FIFO16', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('RAMB16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
|
|
|
|
Cell('RAMB32_S64_ECC', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
# Virtex 5.
|
|
|
|
Cell('FIFO18', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('FIFO18_36', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('FIFO36', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('FIFO36_72', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('RAMB18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
|
|
|
|
Cell('RAMB36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
|
|
|
|
Cell('RAMB18SDP', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('RAMB36SDP', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
# Virtex 6 / Series 7.
|
|
|
|
Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
2020-02-27 12:33:04 -06:00
|
|
|
#Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}),
|
|
|
|
#Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
# Ultrascale.
|
|
|
|
Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
|
2019-09-14 19:49:53 -05:00
|
|
|
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
# Ultra RAM.
|
|
|
|
Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
|
|
Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}),
|
2019-09-14 19:49:53 -05:00
|
|
|
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
# Multipliers and DSP.
|
2019-11-17 20:47:56 -06:00
|
|
|
# Cell('MULT18X18'), # Virtex 2, Spartan 3
|
|
|
|
# Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3
|
|
|
|
# Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E
|
|
|
|
# Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP
|
|
|
|
# Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6
|
2019-11-21 06:05:30 -06:00
|
|
|
# Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
Cell('DSP48E', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 5
|
|
|
|
#Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 6 / Series 7
|
|
|
|
Cell('DSP48E2', port_attrs={'CLK': ['clkbuf_sink']}), # Ultrascale
|
|
|
|
|
|
|
|
# I/O logic.
|
|
|
|
# Virtex 2, Spartan 3.
|
|
|
|
Cell('IFDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'D': ['iopad_external_pin']}),
|
|
|
|
Cell('IFDDRRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'D': ['iopad_external_pin']}),
|
|
|
|
Cell('OFDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'Q': ['iopad_external_pin']}),
|
|
|
|
Cell('OFDDRRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'Q': ['iopad_external_pin']}),
|
|
|
|
Cell('OFDDRTCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'O': ['iopad_external_pin']}),
|
|
|
|
Cell('OFDDRTRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'O': ['iopad_external_pin']}),
|
|
|
|
# Spartan 3E.
|
|
|
|
Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
|
|
|
|
Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
|
|
|
|
# Virtex 4.
|
|
|
|
Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
|
|
|
|
Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
|
|
|
|
Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
|
|
|
|
Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('IDELAY', port_attrs={'C': ['clkbuf_sink']}),
|
|
|
|
Cell('ISERDES', port_attrs={
|
|
|
|
'CLK': ['clkbuf_sink'],
|
|
|
|
'OCLK': ['clkbuf_sink'],
|
|
|
|
'CLKDIV': ['clkbuf_sink'],
|
|
|
|
}),
|
|
|
|
Cell('OSERDES', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
|
|
|
|
# Virtex 5.
|
|
|
|
Cell('IODELAY', port_attrs={'C': ['clkbuf_sink']}),
|
|
|
|
Cell('ISERDES_NODELAY', port_attrs={
|
|
|
|
'CLK': ['clkbuf_sink'],
|
|
|
|
'CLKB': ['clkbuf_sink'],
|
|
|
|
'OCLK': ['clkbuf_sink'],
|
|
|
|
'CLKDIV': ['clkbuf_sink'],
|
|
|
|
}),
|
|
|
|
# Virtex 6.
|
|
|
|
Cell('IODELAYE1', port_attrs={'C': ['clkbuf_sink']}),
|
|
|
|
Cell('ISERDESE1', port_attrs={
|
|
|
|
'CLK': ['clkbuf_sink'],
|
|
|
|
'CLKB': ['clkbuf_sink'],
|
|
|
|
'OCLK': ['clkbuf_sink'],
|
|
|
|
'CLKDIV': ['clkbuf_sink'],
|
|
|
|
}),
|
|
|
|
Cell('OSERDESE1', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
|
|
|
|
# Series 7.
|
|
|
|
Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}),
|
|
|
|
Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}),
|
|
|
|
Cell('ISERDESE2', port_attrs={
|
|
|
|
'CLK': ['clkbuf_sink'],
|
|
|
|
'CLKB': ['clkbuf_sink'],
|
|
|
|
'OCLK': ['clkbuf_sink'],
|
|
|
|
'OCLKB': ['clkbuf_sink'],
|
|
|
|
'CLKDIV': ['clkbuf_sink'],
|
|
|
|
'CLKDIVP': ['clkbuf_sink'],
|
|
|
|
}),
|
|
|
|
Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
|
|
|
|
Cell('PHASER_IN'),
|
|
|
|
Cell('PHASER_IN_PHY'),
|
|
|
|
Cell('PHASER_OUT'),
|
|
|
|
Cell('PHASER_OUT_PHY'),
|
|
|
|
Cell('PHASER_REF'),
|
|
|
|
Cell('PHY_CONTROL'),
|
|
|
|
# Ultrascale.
|
|
|
|
Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
|
|
|
|
Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}),
|
|
|
|
Cell('IDELAYE3', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
|
|
Cell('ODELAYE3', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
|
|
Cell('ISERDESE3', port_attrs={
|
|
|
|
'CLK': ['clkbuf_sink'],
|
|
|
|
'CLK_B': ['clkbuf_sink'],
|
|
|
|
'FIFO_RD_CLK': ['clkbuf_sink'],
|
|
|
|
'CLKDIV': ['clkbuf_sink'],
|
|
|
|
}),
|
|
|
|
Cell('OSERDESE3', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
|
2019-09-14 19:49:53 -05:00
|
|
|
Cell('BITSLICE_CONTROL', keep=True),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
Cell('RIU_OR'),
|
|
|
|
Cell('RX_BITSLICE'),
|
|
|
|
Cell('RXTX_BITSLICE'),
|
|
|
|
Cell('TX_BITSLICE'),
|
|
|
|
Cell('TX_BITSLICE_TRI'),
|
|
|
|
# Spartan 6.
|
|
|
|
Cell('IODELAY2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
|
|
|
|
Cell('IODRP2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
|
|
|
|
Cell('IODRP2_MCB', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
|
|
|
|
Cell('ISERDES2', port_attrs={
|
|
|
|
'CLK0': ['clkbuf_sink'],
|
|
|
|
'CLK1': ['clkbuf_sink'],
|
|
|
|
'CLKDIV': ['clkbuf_sink'],
|
|
|
|
}),
|
|
|
|
Cell('OSERDES2', port_attrs={
|
|
|
|
'CLK0': ['clkbuf_sink'],
|
|
|
|
'CLK1': ['clkbuf_sink'],
|
|
|
|
'CLKDIV': ['clkbuf_sink'],
|
|
|
|
}),
|
|
|
|
|
|
|
|
# I/O buffers.
|
|
|
|
# Input.
|
2019-09-14 19:49:53 -05:00
|
|
|
# Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
Cell('IBUF_DLY_ADJ', port_attrs={'I': ['iopad_external_pin']}),
|
2019-09-14 19:49:53 -05:00
|
|
|
Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
|
|
|
|
Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
Cell('IBUF_ANALOG', port_attrs={'I': ['iopad_external_pin']}),
|
|
|
|
Cell('IBUFE3', port_attrs={'I': ['iopad_external_pin']}),
|
2019-09-14 19:49:53 -05:00
|
|
|
Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
Cell('IBUFDS_DLY_ADJ', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
2019-09-14 19:49:53 -05:00
|
|
|
Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
Cell('IBUFDSE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
Cell('IBUFDS_DPHY', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
# Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
|
|
|
|
Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
# I/O.
|
2019-11-25 22:04:28 -06:00
|
|
|
# Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
|
2019-09-14 19:49:53 -05:00
|
|
|
Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
|
|
|
|
Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}),
|
2019-09-14 19:49:53 -05:00
|
|
|
Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
|
|
|
|
Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
2019-09-14 19:49:53 -05:00
|
|
|
Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
|
|
|
Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
|
|
|
Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
2020-02-27 04:21:01 -06:00
|
|
|
Cell('IOBUFDSE3', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
# Output.
|
2019-09-14 19:49:53 -05:00
|
|
|
# Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
|
|
|
|
Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
|
|
|
Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
# Output + tristate.
|
2019-11-25 22:04:28 -06:00
|
|
|
# Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
|
2019-09-14 19:49:53 -05:00
|
|
|
Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
# Pulls.
|
|
|
|
Cell('KEEPER'),
|
2019-09-14 19:49:53 -05:00
|
|
|
Cell('PULLDOWN'),
|
|
|
|
Cell('PULLUP'),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
# Misc.
|
|
|
|
Cell('DCIRESET', keep=True),
|
|
|
|
Cell('HPIO_VREF'), # Ultrascale
|
2019-09-14 19:49:53 -05:00
|
|
|
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
# Clock buffers (global).
|
|
|
|
# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
#Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFGMUX_VIRTEX4', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFG_GT', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFG_GT_SYNC'),
|
|
|
|
Cell('BUFG_PS', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFGCE_DIV', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
#Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
|
|
|
|
# Clock buffers (IO) -- Spartan 6.
|
|
|
|
Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}),
|
2019-11-29 09:55:29 -06:00
|
|
|
Cell('BUFPLL', port_attrs={'IOCLK': ['clkbuf_driver']}),
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}),
|
|
|
|
|
|
|
|
# Clock buffers (IO and regional) -- Virtex.
|
|
|
|
Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFIODQS', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}),
|
|
|
|
|
|
|
|
# Clock components.
|
|
|
|
# VIrtex.
|
|
|
|
# TODO: CLKDLL
|
|
|
|
# TODO: CLKDLLE
|
|
|
|
# TODO: CLKDLLHF
|
|
|
|
# Virtex 2, Spartan 3.
|
|
|
|
Cell('DCM'),
|
|
|
|
# Spartan 3E.
|
|
|
|
Cell('DCM_SP'),
|
|
|
|
# Spartan 6 (also uses DCM_SP and PLL_BASE).
|
|
|
|
Cell('DCM_CLKGEN'),
|
|
|
|
# Virtex 4/5.
|
|
|
|
Cell('DCM_ADV'),
|
|
|
|
Cell('DCM_BASE'),
|
|
|
|
Cell('DCM_PS'),
|
|
|
|
# Virtex 4.
|
|
|
|
Cell('PMCD'),
|
|
|
|
# Virtex 5.
|
|
|
|
Cell('PLL_ADV'),
|
|
|
|
Cell('PLL_BASE'),
|
|
|
|
# Virtex 6.
|
|
|
|
Cell('MMCM_ADV'),
|
|
|
|
Cell('MMCM_BASE'),
|
|
|
|
# Series 7.
|
|
|
|
Cell('MMCME2_ADV'),
|
|
|
|
Cell('MMCME2_BASE'),
|
|
|
|
Cell('PLLE2_ADV'),
|
|
|
|
Cell('PLLE2_BASE'),
|
|
|
|
# Ultrascale.
|
|
|
|
Cell('MMCME3_ADV'),
|
|
|
|
Cell('MMCME3_BASE'),
|
|
|
|
Cell('PLLE3_ADV'),
|
|
|
|
Cell('PLLE3_BASE'),
|
|
|
|
# Ultrascale+.
|
|
|
|
Cell('MMCME4_ADV'),
|
|
|
|
Cell('MMCME4_BASE'),
|
|
|
|
Cell('PLLE4_ADV'),
|
|
|
|
Cell('PLLE4_BASE'),
|
|
|
|
|
|
|
|
# Misc stuff.
|
|
|
|
Cell('BUFT'),
|
|
|
|
# Series 7 I/O FIFOs.
|
|
|
|
Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
|
|
# Ultrascale special synchronizer register.
|
2019-09-14 19:49:53 -05:00
|
|
|
Cell('HARD_SYNC', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
|
|
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
# Singletons.
|
|
|
|
# Startup.
|
|
|
|
# TODO: STARTUP_VIRTEX
|
|
|
|
# TODO: STARTUP_VIRTEX2
|
|
|
|
Cell('STARTUP_SPARTAN3', keep=True),
|
|
|
|
Cell('STARTUP_SPARTAN3E', keep=True),
|
|
|
|
Cell('STARTUP_SPARTAN3A', keep=True),
|
|
|
|
Cell('STARTUP_SPARTAN6', keep=True),
|
|
|
|
Cell('STARTUP_VIRTEX4', keep=True),
|
|
|
|
Cell('STARTUP_VIRTEX5', keep=True),
|
|
|
|
Cell('STARTUP_VIRTEX6', keep=True),
|
|
|
|
Cell('STARTUPE2', keep=True), # Series 7
|
|
|
|
Cell('STARTUPE3', keep=True), # Ultrascale
|
|
|
|
# Capture trigger.
|
|
|
|
# TODO: CAPTURE_VIRTEX
|
|
|
|
# TODO: CAPTURE_VIRTEX2
|
|
|
|
Cell('CAPTURE_SPARTAN3', keep=True),
|
|
|
|
Cell('CAPTURE_SPARTAN3A', keep=True),
|
|
|
|
Cell('CAPTURE_VIRTEX4', keep=True),
|
|
|
|
Cell('CAPTURE_VIRTEX5', keep=True),
|
|
|
|
Cell('CAPTURE_VIRTEX6', keep=True),
|
|
|
|
Cell('CAPTUREE2', keep=True), # Series 7
|
|
|
|
# Internal Configuration Access Port.
|
|
|
|
# TODO: ICAP_VIRTEX2
|
|
|
|
Cell('ICAP_SPARTAN3A', keep=True),
|
|
|
|
Cell('ICAP_SPARTAN6', keep=True),
|
|
|
|
Cell('ICAP_VIRTEX4', keep=True),
|
|
|
|
Cell('ICAP_VIRTEX5', keep=True),
|
|
|
|
Cell('ICAP_VIRTEX6', keep=True),
|
|
|
|
Cell('ICAPE2', keep=True), # Series 7
|
|
|
|
Cell('ICAPE3', keep=True), # Ultrascale
|
|
|
|
# JTAG.
|
|
|
|
# TODO: BSCAN_VIRTEX
|
|
|
|
# TODO: BSCAN_VIRTEX2
|
|
|
|
Cell('BSCAN_SPARTAN3', keep=True),
|
|
|
|
Cell('BSCAN_SPARTAN3A', keep=True),
|
|
|
|
Cell('BSCAN_SPARTAN6', keep=True),
|
|
|
|
Cell('BSCAN_VIRTEX4', keep=True),
|
|
|
|
Cell('BSCAN_VIRTEX5', keep=True),
|
|
|
|
Cell('BSCAN_VIRTEX6', keep=True),
|
|
|
|
Cell('BSCANE2', keep=True), # Series 7, Ultrascale
|
|
|
|
# DNA port.
|
|
|
|
Cell('DNA_PORT'), # Virtex 5/6, Series 7, Spartan 3A/6
|
|
|
|
Cell('DNA_PORTE2'), # Ultrascale
|
|
|
|
# Frame ECC.
|
|
|
|
Cell('FRAME_ECC_VIRTEX4'),
|
|
|
|
Cell('FRAME_ECC_VIRTEX5'),
|
|
|
|
Cell('FRAME_ECC_VIRTEX6'),
|
|
|
|
Cell('FRAME_ECCE2'), # Series 7
|
|
|
|
Cell('FRAME_ECCE3'), # Ultrascale
|
|
|
|
# AXSS command access.
|
|
|
|
Cell('USR_ACCESS_VIRTEX4'),
|
|
|
|
Cell('USR_ACCESS_VIRTEX5'),
|
|
|
|
Cell('USR_ACCESS_VIRTEX6'),
|
|
|
|
Cell('USR_ACCESSE2'), # Series 7, Ultrascale
|
|
|
|
# Misc.
|
|
|
|
Cell('POST_CRC_INTERNAL'), # Spartan 6
|
|
|
|
Cell('SUSPEND_SYNC', keep=True), # Spartan 6
|
|
|
|
Cell('KEY_CLEAR', keep=True), # Virtex 5
|
|
|
|
Cell('MASTER_JTAG', keep=True), # Ultrascale
|
|
|
|
Cell('SPI_ACCESS', keep=True), # Spartan 3AN
|
|
|
|
Cell('EFUSE_USR'),
|
|
|
|
|
|
|
|
# ADC.
|
|
|
|
Cell('SYSMON'), # Virtex 5/6
|
|
|
|
Cell('XADC'), # Series 7
|
|
|
|
Cell('SYSMONE1'), # Ultrascale
|
|
|
|
Cell('SYSMONE4'), # Ultrascale+
|
|
|
|
|
|
|
|
# Gigabit transceivers.
|
|
|
|
# Spartan 6.
|
|
|
|
Cell('GTPA1_DUAL'),
|
|
|
|
# Virtex 2 Pro.
|
|
|
|
# TODO: GT_*
|
|
|
|
# TODO: GT10_*
|
|
|
|
# Virtex 4.
|
|
|
|
Cell('GT11_CUSTOM'),
|
|
|
|
Cell('GT11_DUAL'),
|
|
|
|
Cell('GT11CLK'),
|
|
|
|
Cell('GT11CLK_MGT'),
|
|
|
|
# Virtex 5.
|
|
|
|
Cell('GTP_DUAL'),
|
|
|
|
Cell('GTX_DUAL'),
|
|
|
|
Cell('CRC32', port_attrs={'CRCCLK': ['clkbuf_sink']}),
|
|
|
|
Cell('CRC64', port_attrs={'CRCCLK': ['clkbuf_sink']}),
|
|
|
|
# Virtex 6.
|
|
|
|
Cell('GTHE1_QUAD'),
|
|
|
|
Cell('GTXE1'),
|
|
|
|
Cell('IBUFDS_GTXE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
Cell('IBUFDS_GTHE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
# Series 7.
|
|
|
|
Cell('GTHE2_CHANNEL'),
|
|
|
|
Cell('GTHE2_COMMON'),
|
|
|
|
Cell('GTPE2_CHANNEL'),
|
|
|
|
Cell('GTPE2_COMMON'),
|
|
|
|
Cell('GTXE2_CHANNEL'),
|
|
|
|
Cell('GTXE2_COMMON'),
|
|
|
|
Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
# Ultrascale.
|
|
|
|
Cell('GTHE3_CHANNEL'),
|
|
|
|
Cell('GTHE3_COMMON'),
|
|
|
|
Cell('GTHE4_CHANNEL'),
|
|
|
|
Cell('GTHE4_COMMON'),
|
|
|
|
Cell('GTYE3_CHANNEL'),
|
|
|
|
Cell('GTYE3_COMMON'),
|
|
|
|
Cell('GTYE4_CHANNEL'),
|
|
|
|
Cell('GTYE4_COMMON'),
|
|
|
|
Cell('IBUFDS_GTE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
|
|
Cell('OBUFDS_GTE3', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
|
|
|
Cell('OBUFDS_GTE3_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
|
|
|
Cell('OBUFDS_GTE4', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
|
|
|
Cell('OBUFDS_GTE4_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
|
|
|
|
|
|
|
# PCIE IP.
|
|
|
|
Cell('PCIE_A1'), # Spartan 6
|
|
|
|
Cell('PCIE_EP'), # Virtex 5
|
|
|
|
Cell('PCIE_2_0'), # Virtex 6
|
|
|
|
Cell('PCIE_2_1'), # Series 7
|
|
|
|
Cell('PCIE_3_0'), # Series 7
|
|
|
|
Cell('PCIE_3_1'), # Ultrascale
|
|
|
|
Cell('PCIE40E4'), # Ultrascale+
|
|
|
|
|
|
|
|
# Ethernet IP.
|
|
|
|
Cell('EMAC'), # Virtex 4
|
|
|
|
Cell('TEMAC'), # Virtex 5
|
|
|
|
Cell('TEMAC_SINGLE'), # Virtex 6
|
|
|
|
Cell('CMAC'), # Ultrascale
|
|
|
|
Cell('CMACE4'), # Ultrsacale+
|
|
|
|
|
|
|
|
# PowerPC.
|
|
|
|
# TODO PPC405 (Virtex 2)
|
|
|
|
Cell('PPC405_ADV'), # Virtex 4
|
|
|
|
Cell('PPC440'), # Virtex 5
|
|
|
|
|
|
|
|
# Misc hard IP.
|
|
|
|
Cell('MCB'), # Spartan 6 Memory Controller Block
|
|
|
|
Cell('PS7', keep=True), # The Zynq 7000 ARM Processor System.
|
|
|
|
Cell('PS8', keep=True), # The Zynq Ultrascale+ ARM Processor System.
|
|
|
|
Cell('ILKN'), # Ultrascale Interlaken
|
|
|
|
Cell('ILKNE4'), # Ultrascale+ Interlaken
|
2019-08-13 14:36:59 -05:00
|
|
|
]
|
|
|
|
|
2019-09-14 19:49:53 -05:00
|
|
|
|
2019-08-13 14:36:59 -05:00
|
|
|
class State(Enum):
|
|
|
|
OUTSIDE = auto()
|
|
|
|
IN_MODULE = auto()
|
|
|
|
IN_OTHER_MODULE = auto()
|
|
|
|
IN_FUNCTION = auto()
|
|
|
|
IN_TASK = auto()
|
|
|
|
|
|
|
|
def xtract_cell_decl(cell, dirs, outf):
|
|
|
|
for dir in dirs:
|
|
|
|
fname = os.path.join(dir, cell.name + '.v')
|
|
|
|
try:
|
|
|
|
with open(fname) as f:
|
|
|
|
state = State.OUTSIDE
|
|
|
|
found = False
|
|
|
|
# Probably the most horrible Verilog "parser" ever written.
|
2019-08-28 10:28:01 -05:00
|
|
|
module_ports = []
|
|
|
|
invertible_ports = set()
|
2019-08-13 14:36:59 -05:00
|
|
|
for l in f:
|
|
|
|
l = l.partition('//')[0]
|
|
|
|
l = l.strip()
|
|
|
|
if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)):
|
|
|
|
if found:
|
|
|
|
print('Multiple modules in {}.'.format(fname))
|
|
|
|
sys.exit(1)
|
|
|
|
elif state != State.OUTSIDE:
|
|
|
|
print('Nested modules in {}.'.format(fname))
|
|
|
|
sys.exit(1)
|
|
|
|
found = True
|
|
|
|
state = State.IN_MODULE
|
|
|
|
if cell.keep:
|
|
|
|
outf.write('(* keep *)\n')
|
|
|
|
outf.write('module {} (...);\n'.format(cell.name))
|
|
|
|
elif l.startswith('module '):
|
|
|
|
if state != State.OUTSIDE:
|
|
|
|
print('Nested modules in {}.'.format(fname))
|
|
|
|
sys.exit(1)
|
|
|
|
state = State.IN_OTHER_MODULE
|
|
|
|
elif l.startswith('task '):
|
|
|
|
if state == State.IN_MODULE:
|
|
|
|
state = State.IN_TASK
|
|
|
|
elif l.startswith('function '):
|
|
|
|
if state == State.IN_MODULE:
|
|
|
|
state = State.IN_FUNCTION
|
|
|
|
elif l == 'endtask':
|
|
|
|
if state == State.IN_TASK:
|
|
|
|
state = State.IN_MODULE
|
|
|
|
elif l == 'endfunction':
|
|
|
|
if state == State.IN_FUNCTION:
|
|
|
|
state = State.IN_MODULE
|
|
|
|
elif l == 'endmodule':
|
|
|
|
if state == State.IN_MODULE:
|
2019-08-28 10:28:01 -05:00
|
|
|
for kind, rng, port in module_ports:
|
|
|
|
for attr in cell.port_attrs.get(port, []):
|
|
|
|
outf.write(' (* {} *)\n'.format(attr))
|
|
|
|
if port in invertible_ports:
|
|
|
|
outf.write(' (* invertible_pin = "IS_{}_INVERTED" *)\n'.format(port))
|
|
|
|
if rng is None:
|
|
|
|
outf.write(' {} {};\n'.format(kind, port))
|
|
|
|
else:
|
|
|
|
outf.write(' {} {} {};\n'.format(kind, rng, port))
|
2019-08-13 14:36:59 -05:00
|
|
|
outf.write(l + '\n')
|
|
|
|
outf.write('\n')
|
|
|
|
elif state != State.IN_OTHER_MODULE:
|
|
|
|
print('endmodule in weird place in {}.'.format(cell.name, fname))
|
|
|
|
sys.exit(1)
|
|
|
|
state = State.OUTSIDE
|
|
|
|
elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
|
|
|
|
if l.endswith((';', ',')):
|
|
|
|
l = l[:-1]
|
|
|
|
if ';' in l:
|
|
|
|
print('Weird port line in {} [{}].'.format(fname, l))
|
|
|
|
sys.exit(1)
|
|
|
|
kind, _, ports = l.partition(' ')
|
|
|
|
for port in ports.split(','):
|
|
|
|
port = port.strip()
|
2019-08-28 10:28:01 -05:00
|
|
|
if port.startswith('['):
|
|
|
|
rng, port = port.split()
|
|
|
|
else:
|
|
|
|
rng = None
|
|
|
|
module_ports.append((kind, rng, port))
|
2019-08-13 14:36:59 -05:00
|
|
|
elif l.startswith('parameter ') and state == State.IN_MODULE:
|
|
|
|
if 'UNPLACED' in l:
|
|
|
|
continue
|
|
|
|
if l.endswith((';', ',')):
|
|
|
|
l = l[:-1]
|
|
|
|
while ' ' in l:
|
|
|
|
l = l.replace(' ', ' ')
|
|
|
|
if ';' in l:
|
|
|
|
print('Weird parameter line in {} [{}].'.format(fname, l))
|
|
|
|
sys.exit(1)
|
|
|
|
outf.write(' {};\n'.format(l))
|
2019-08-28 10:28:01 -05:00
|
|
|
match = re.search('IS_([a-zA-Z0-9_]+)_INVERTED', l)
|
|
|
|
if match:
|
|
|
|
invertible_ports.add(match[1])
|
2019-08-13 14:36:59 -05:00
|
|
|
if state != State.OUTSIDE:
|
|
|
|
print('endmodule not found in {}.'.format(fname))
|
|
|
|
sys.exit(1)
|
|
|
|
if not found:
|
|
|
|
print('Cannot find module {} in {}.'.format(cell.name, fname))
|
|
|
|
sys.exit(1)
|
|
|
|
return
|
|
|
|
except FileNotFoundError:
|
|
|
|
continue
|
|
|
|
print('Cannot find {}.'.format(cell.name))
|
|
|
|
sys.exit(1)
|
|
|
|
|
|
|
|
if __name__ == '__main__':
|
2019-09-14 19:49:53 -05:00
|
|
|
parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from ISE and Vivado.')
|
2019-08-13 14:36:59 -05:00
|
|
|
parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1')
|
2019-09-14 19:49:53 -05:00
|
|
|
parser.add_argument('ise_dir', nargs='?', default='/opt/Xilinx/ISE/14.7')
|
2019-08-13 14:36:59 -05:00
|
|
|
args = parser.parse_args()
|
|
|
|
|
|
|
|
dirs = [
|
|
|
|
os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'),
|
|
|
|
os.path.join(args.vivado_dir, 'data/verilog/src/retarget'),
|
2019-09-14 19:49:53 -05:00
|
|
|
os.path.join(args.ise_dir, 'ISE_DS/ISE/verilog/xeclib/unisims'),
|
2019-08-13 14:36:59 -05:00
|
|
|
]
|
|
|
|
for dir in dirs:
|
|
|
|
if not os.path.isdir(dir):
|
|
|
|
print('{} is not a directory'.format(dir))
|
|
|
|
|
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-01 09:00:15 -05:00
|
|
|
out = StringIO()
|
|
|
|
for cell in CELLS:
|
|
|
|
xtract_cell_decl(cell, dirs, out)
|
|
|
|
|
|
|
|
with open('cells_xtra.v', 'w') as f:
|
|
|
|
f.write('// Created by cells_xtra.py from Xilinx models\n')
|
|
|
|
f.write('\n')
|
|
|
|
f.write(out.getvalue())
|