mirror of https://github.com/YosysHQ/yosys.git
21 lines
497 B
Plaintext
21 lines
497 B
Plaintext
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# loop involving asynchronous memory ports
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design -reset
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read -vlog2k <<EOF
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module pingpong(input wire [1:0] x, output wire [3:0] y1, output wire [3:0] y2);
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reg [3:0] mem [15:0];
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reg [5:0] i;
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initial begin
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for (i = 0; i < 16; i = i + 1)
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mem[i] = i * 371;
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end
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assign y1 = mem[{y2[3:2], x}];
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assign y2 = mem[y1];
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endmodule
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EOF
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hierarchy -top pingpong
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prep
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logger -nowarn "found logic loop in module pingpong:"
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logger -expect error "Found \d+ problems in 'check -assert'" 1
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check -assert
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