mirror of https://github.com/YosysHQ/yosys.git
36 lines
642 B
Plaintext
36 lines
642 B
Plaintext
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read_verilog <<EOT
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module top(input a, b, output o);
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wire tmp;
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assign o = tmp | 1'bx;
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assign tmp = a & 1'b0;
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endmodule
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EOT
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design -save read
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select -assert-count 1 t:$and
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select -assert-count 1 t:$or
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opt_expr
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select -assert-none t:$and t:$or
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sat -verify -enable_undef -prove o 1'bx
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design -load read
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opt_expr -keepdc
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select -assert-none t:$and t:$or
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sat -verify -enable_undef -prove o 1'bx
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design -load read
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simplemap
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opt_expr -keepdc
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select -assert-none t:$_AND_ t:$_OR_
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sat -verify -enable_undef -prove o 1'bx
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design -load read
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simplemap
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opt_expr -keepdc
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select -assert-none t:$_AND_ t:$_OR_
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sat -verify -enable_undef -prove o 1'bx
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