yosys/tests/lut/check_map.ys

mirror of https://github.com/YosysHQ/yosys.git
simplemap
equiv_opt -assert techmap -map +/gate2lut.v -D LUT_WIDTH=4
design -load postopt
select -assert-count 1 t:$lut
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-04 22:50:38 -06:00			`simplemap`
equiv_opt: new command, for verifying optimization passes. 2018-12-06 08:28:20 -06:00			`equiv_opt -assert techmap -map +/gate2lut.v -D LUT_WIDTH=4`
			`design -load postopt`
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-04 22:50:38 -06:00			`select -assert-count 1 t:$lut`