mirror of https://github.com/YosysHQ/yosys.git
45 lines
753 B
Verilog
45 lines
753 B
Verilog
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module top;
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function automatic [31:0] operation1;
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input [4:0] rounds;
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input integer num;
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integer i;
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begin
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begin : shadow
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integer rounds;
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rounds = 0;
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end
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for (i = 0; i < rounds; i = i + 1)
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num = num * 2;
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operation1 = num;
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end
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endfunction
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function automatic [31:0] operation2;
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input [4:0] var;
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input integer num;
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begin
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var[0] = var[0] ^ 1;
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operation2 = num * var;
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end
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endfunction
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wire [31:0] a;
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assign a = 2;
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parameter A = 3;
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wire [31:0] x1;
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assign x1 = operation1(A, a);
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wire [31:0] x2;
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assign x2 = operation2(A, a);
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// `define VERIFY
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`ifdef VERIFY
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assert property (a == 2);
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assert property (A == 3);
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assert property (x1 == 16);
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assert property (x2 == 4);
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`endif
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endmodule
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