mirror of https://github.com/YosysHQ/yosys.git
12 lines
630 B
Verilog
12 lines
630 B
Verilog
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// Async Active Low Reset DFF
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module \$_DFFE_PN0P_ (input D, C, R, E, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) begin
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dffeas #(.is_wysiwyg("TRUE"), .power_up("high")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(E), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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end else begin
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dffeas #(.is_wysiwyg("TRUE"), .power_up("low")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(E), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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end
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endgenerate
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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