yosys/tests/various/abc9.ys

read_verilog abc9.v
design -save read
hierarchy -top abc9_test027
proc
design -save gold

abc9 -lut 4
check
design -stash gate

design -import gold -as gold
design -import gate -as gate

miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter


design -load read
hierarchy -top abc9_test028
proc

abc9 -lut 4
select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
select -assert-count 1 t:unknown
select -assert-none t:$lut t:unknown %% t: %D


design -load read
hierarchy -top abc9_test032
proc
clk2fflogic
design -save gold

abc9 -lut 4
check
design -stash gate

design -import gold -as gold
design -import gate -as gate

miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -seq 10 -verify -prove-asserts -show-ports miter


design -reset
read_verilog -icells <<EOT
module abc9_test036(input clk, d, output q);
(* keep *) reg w;
$__ABC9_FF_ ff(.D(d), .Q(w));
wire \ff.clock = clk;
wire \ff.init = 1'b0;
assign q = w;
endmodule
EOT
abc9 -lut 4 -dff


design -reset
read_verilog -icells -specify <<EOT
(* abc9_lut=1, blackbox *)
module LUT2(input [1:0] i, output o);
parameter [3:0] mask = 0;
assign o = i[0] ? (i[1] ? mask[3] : mask[2])
                : (i[1] ? mask[1] : mask[0]);
specify
  (i *> o) = 1;
endspecify
endmodule

module top(input [1:0] i, output o);
LUT2 #(.mask(4'b0)) lut (.i(i), .o(o));
endmodule
EOT
abc9