yosys/tests/techmap/kogge-stone.tcl

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yosys -import
read_verilog +/choices/kogge-stone.v
read_verilog lcu_refined.v
design -save init
for {set i 1} {$i <= 16} {incr i} {
design -load init
chparam -set WIDTH $i
yosys proc
equiv_make -blacklist ppa.nomatch lcu _80_lcu_kogge_stone equiv
equiv_simple equiv
equiv_status -assert equiv
}