mirror of https://github.com/YosysHQ/yosys.git
11 lines
132 B
Verilog
11 lines
132 B
Verilog
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module simple_function();
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function myfunction;
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input a, b, c, d;
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begin
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myfunction = ((a+b) + (c-d));
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end
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endfunction
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endmodule
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