mirror of https://github.com/YosysHQ/yosys.git
16 lines
217 B
Verilog
16 lines
217 B
Verilog
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module reg_seq_example( clk, reset, d, q);
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input clk, reset, d;
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output q;
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reg q;
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wire clk, reset, d;
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always @ (posedge clk or posedge reset)
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if (reset) begin
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q <= 1'b0;
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end else begin
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q <= d;
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end
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endmodule
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