mirror of https://github.com/YosysHQ/yosys.git
21 lines
575 B
Verilog
21 lines
575 B
Verilog
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//-----------------------------------------------------
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// Design Name : full_subtracter_gates
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// File Name : full_subtracter_gates.v
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// Function : Full Subtracter Using Gates
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module full_subtracter_gates(x,y,z,difference,borrow);
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input x,y,z;
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output difference,borrow;
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wire inv_x,borrow1,borrow2,borrow3;
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not (inv_x,x);
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and U_borrow1 (borrow1,inv_x,y),
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U_borrow2 (borrow2,inv_x,z),
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U_borrow3 (borrow3,y,z);
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xor U_diff (difference,borrow1,borrow2,borrows);
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endmodule
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