mirror of https://github.com/YosysHQ/yosys.git
34 lines
1.1 KiB
Verilog
34 lines
1.1 KiB
Verilog
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//==========================================
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// Function : Code Gray counter.
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// Coder : Alex Claros F.
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// Date : 15/May/2005.
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//=======================================
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module GrayCounter
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#(parameter COUNTER_WIDTH = 4)
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(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
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input wire Enable_in, //Count enable.
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input wire Clear_in, //Count reset.
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input wire Clk);
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/////////Internal connections & variables///////
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reg [COUNTER_WIDTH-1:0] BinaryCount;
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/////////Code///////////////////////
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always @ (posedge Clk)
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if (Clear_in) begin
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BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
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GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_in'.
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end
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else if (Enable_in) begin
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BinaryCount <= BinaryCount + 1;
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GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
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BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
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end
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endmodule
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