mirror of https://github.com/YosysHQ/yosys.git
26 lines
502 B
Plaintext
26 lines
502 B
Plaintext
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read_verilog <<EOT
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module register_file(
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input wire clk,
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input wire write_enable,
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input wire [63:0] write_data,
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input wire [4:0] write_reg,
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input wire [4:0] read1_reg,
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output reg [63:0] read1_data,
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);
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reg [63:0] registers[0:31];
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always @(posedge clk) begin
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if (write_enable == 1'b1) begin
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registers[write_reg] <= write_data;
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end
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end
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always @(all) begin
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read1_data <= registers[read1_reg];
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end
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endmodule
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EOT
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synth_ecp5 -abc9
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