mirror of https://github.com/YosysHQ/yosys.git
23 lines
378 B
Plaintext
23 lines
378 B
Plaintext
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read_ilang << EOT
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module \top
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wire width 4 input 1 \a
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wire width 2 input 2 \b
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wire input 3 \clk
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wire width 4 output 4 \q
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wire input 5 \en
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wire width 4 \nq
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process \p
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assign \nq \a
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assign \nq [1:0] \b
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switch \en
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case 1'1
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assign \nq [3] 1'0
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end
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sync posedge \clk
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update \q \nq
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end
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end
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EOT
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proc
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check -assert
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