mirror of https://github.com/YosysHQ/yosys.git
100 lines
2.6 KiB
Verilog
100 lines
2.6 KiB
Verilog
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// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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(* techmap_celltype = "$alu" *)
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module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 2;
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parameter B_WIDTH = 2;
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parameter Y_WIDTH = 2;
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parameter _TECHMAP_CONSTVAL_CI_ = 0;
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parameter _TECHMAP_CONSTMSK_CI_ = 0;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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genvar i;
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wire co;
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(* force_downto *)
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//wire [Y_WIDTH-1:0] C = {CO, CI};
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wire [Y_WIDTH:0] C;
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(* force_downto *)
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wire [Y_WIDTH-1:0] S = {AA ^ BB};
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assign CO[Y_WIDTH-1:0] = C[Y_WIDTH:1];
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//assign CO[Y_WIDTH-1] = co;
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generate
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adder_carry intermediate_adder (
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.cin ( ),
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.cout (C[0]),
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.p (1'b0),
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.g (CI),
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.sumout ()
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);
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endgenerate
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genvar i;
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generate if (Y_WIDTH > 2) begin
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for (i = 0; i < Y_WIDTH-2; i = i + 1) begin:slice
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adder_carry my_adder (
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.cin(C[i]),
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.g(AA[i]),
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.p(S[i]),
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.cout(C[i+1]),
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.sumout(Y[i])
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);
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end
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end endgenerate
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generate
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adder_carry final_adder (
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.cin (C[Y_WIDTH-2]),
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.cout (),
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.p (1'b0),
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.g (1'b0),
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.sumout (co)
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);
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endgenerate
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assign Y[Y_WIDTH-2] = S[Y_WIDTH-2] ^ co;
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assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2];
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assign Y[Y_WIDTH-1] = S[Y_WIDTH-1] ^ C[Y_WIDTH-1];
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assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1];
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assign X = S;
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endmodule
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