yosys/tests/opt/opt_expr_cmp.ys

mirror of https://github.com/YosysHQ/yosys.git
read_verilog opt_expr_cmp.v
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 0 t:$gt t:$ge t:$lt t:$le
opt_expr: simplify any unsigned comparisons with all-0 and all-1. Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input. 2019-01-01 20:45:49 -06:00			`read_verilog opt_expr_cmp.v`
			`equiv_opt -assert opt_expr -fine`
			`design -load postopt`
			`select -assert-count 0 t:$gt t:$ge t:$lt t:$le`