mirror of https://github.com/YosysHQ/yosys.git
26 lines
751 B
Plaintext
26 lines
751 B
Plaintext
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read_verilog <<EOT
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module simd(input [12*4-1:0] a, input [12*4-1:0] b, (* use_dsp="simd" *) output [7*12-1:0] o12, (* use_dsp="simd" *) output [2*24-1:0] o24);
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generate
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genvar i;
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// 4 x 12-bit adder
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for (i = 0; i < 4; i++)
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assign o12[i*12+:12] = a[i*12+:12] + b[i*12+:12];
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// 2 x 24-bit subtract
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for (i = 0; i < 2; i++)
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assign o24[i*24+:24] = a[i*24+:24] - b[i*24+:24];
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endgenerate
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reg [3*12-1:0] ro;
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always @* begin
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ro[0*12+:12] = a[0*10+:10] + b[0*10+:10];
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ro[1*12+:12] = a[1*10+:10] + b[1*10+:10];
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ro[2*12+:12] = a[2*8+:8] + b[2*8+:8];
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end
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assign o12[4*12+:3*12] = ro;
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endmodule
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EOT
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proc
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx
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design -load postopt
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select -assert-count 3 t:DSP48E1
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