mirror of https://github.com/YosysHQ/yosys.git
26 lines
571 B
Coq
26 lines
571 B
Coq
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module DFF(input D, CLK, nRSTZ, nSETZ, output reg Q);
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always @(posedge CLK, negedge nRSTZ, negedge nSETZ) begin
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if (!nRSTZ)
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Q <= 1'b0;
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else if (!nSETZ)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule
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module LUT2(input IN0, IN1, output OUT);
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parameter [3:0] INIT = 0;
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assign OUT = INIT[{IN1, IN0}];
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endmodule
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module LUT3(input IN0, IN1, IN2, output OUT);
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parameter [7:0] INIT = 0;
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assign OUT = INIT[{IN2, IN1, IN0}];
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endmodule
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module LUT4(input IN0, IN1, IN2, IN3, output OUT);
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parameter [15:0] INIT = 0;
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assign OUT = INIT[{IN3, IN2, IN1, IN0}];
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endmodule
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