mirror of https://github.com/YosysHQ/yosys.git
32 lines
801 B
Plaintext
32 lines
801 B
Plaintext
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read_verilog <<EOT
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module dds(input clk, output reg [15:0] signal1, output reg [15:0] signal2);
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reg [9:0] phase_accumulator_1;
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reg [9:0] phase_accumulator_2;
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reg [15:0] sine_table [0:255];
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initial begin
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$readmemh("bug1836.mem",sine_table);
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end
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always @(posedge clk) begin
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phase_accumulator_1 <= phase_accumulator_1 + 1;
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phase_accumulator_2 <= phase_accumulator_2 + 2;
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end
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always @(posedge clk) begin
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signal1 <= sine_table[phase_accumulator_1[9:2]];
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//signal2 <= sine_table[phase_accumulator_2[9:2]];
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end
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//comment out this always block below to test for single port read
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always @(posedge clk) begin
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//signal1 <= sine_table[phase_accumulator_1[9:2]];
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signal2 <= sine_table[phase_accumulator_2[9:2]];
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end
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endmodule
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EOT
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synth_ecp5 -top dds
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select -assert-count 1 t:DP16KD
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