yosys/techlibs/xilinx/example_zed_counter/example.ucf

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NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
NET "clk" LOC = Y9 | IOSTANDARD=LVCMOS33; # "GCLK"
NET "ctrl" LOC = P16 | IOSTANDARD=LVCMOS18; # "BTNC"
NET "led_0" LOC = T22 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_1" LOC = T21 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_2" LOC = U22 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_3" LOC = U21 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_4" LOC = V22 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_5" LOC = W22 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_6" LOC = U19 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_7" LOC = U14 | IOSTANDARD=LVCMOS33; # "LD0"