mirror of https://github.com/YosysHQ/yosys.git
11 lines
328 B
Plaintext
11 lines
328 B
Plaintext
|
|
||
|
|
This is a simple example for Yosys synthesis targeting the ZED FPGA
|
||
|
|
development board [1, 2]. Simple script for xst-based synthesis (incl.
|
||
|
|
generation of reference edif files) and uploading to the board can be
|
||
|
|
found here [3].
|
||
|
|
|
||
|
|
[1] http://www.zedboard.org/
|
||
|
|
[2] https://www.xilinx.com/zynq/
|
||
|
|
[3] http://verilog.james.walms.co.uk/
|
||
|
|
|