mirror of https://github.com/YosysHQ/yosys.git
46 lines
1.1 KiB
Verilog
46 lines
1.1 KiB
Verilog
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module LUT_MULTI(
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input [3:0] PORT_R0_ADDR,
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input [3:0] PORT_R1_ADDR,
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input [3:0] PORT_R2_ADDR,
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input [3:0] PORT_R3_ADDR,
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input [3:0] PORT_R4_ADDR,
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input [3:0] PORT_R5_ADDR,
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input [3:0] PORT_R6_ADDR,
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input [3:0] PORT_RW_ADDR,
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input PORT_RW_CLK,
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input PORT_RW_WR_EN,
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input [1:0] PORT_RW_WR_DATA,
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output [1:0] PORT_R0_RD_DATA,
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output [1:0] PORT_R1_RD_DATA,
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output [1:0] PORT_R2_RD_DATA,
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output [1:0] PORT_R3_RD_DATA,
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output [1:0] PORT_R4_RD_DATA,
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output [1:0] PORT_R5_RD_DATA,
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output [1:0] PORT_R6_RD_DATA,
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output [1:0] PORT_RW_RD_DATA
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);
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parameter INIT = 0;
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parameter OPTION_PORTS = "UNDEFINED";
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reg [1:0] mem [0:15];
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integer i;
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initial
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for (i = 0; i < 16; i += 1)
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mem[i] = INIT[i*4+:4];
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assign PORT_R0_RD_DATA = mem[PORT_R0_ADDR];
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assign PORT_R1_RD_DATA = mem[PORT_R1_ADDR];
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assign PORT_R2_RD_DATA = mem[PORT_R2_ADDR];
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assign PORT_R3_RD_DATA = mem[PORT_R3_ADDR];
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assign PORT_R4_RD_DATA = mem[PORT_R4_ADDR];
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assign PORT_R5_RD_DATA = mem[PORT_R5_ADDR];
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assign PORT_R6_RD_DATA = mem[PORT_R6_ADDR];
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assign PORT_RW_RD_DATA = mem[PORT_RW_ADDR];
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always @(posedge PORT_RW_CLK)
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if (PORT_RW_WR_EN)
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mem[PORT_RW_ADDR] <= PORT_RW_WR_DATA;
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endmodule
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