yosys/tests/arch/xilinx/fsm.ys

read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten

equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter

design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module

select -assert-count 1 t:BUFG
select -assert-count 4 t:FDRE
select -assert-count 1 t:FDSE
select -assert-count 1 t:LUT2
select -assert-count 3 t:LUT5
select -assert-count 1 t:LUT6
select -assert-none t:BUFG t:IBUF t:OBUF t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
Share common tests 2019-10-18 05:19:59 -05:00			`read_verilog ../common/fsm.v`
remove not needed top module 2019-10-04 02:41:45 -05:00			`hierarchy -top fsm`
Add smoke tests to tests/xilinx 2019-09-10 00:08:03 -05:00			`proc`
			`flatten`
Fixed tests 2019-11-11 08:41:33 -06:00
			`equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx`
			`miter -equiv -make_assert -flatten gold gate miter`
			`sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter`

Add smoke tests to tests/xilinx 2019-09-10 00:08:03 -05:00			`design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)`
remove not needed top module 2019-10-04 02:41:45 -05:00			`cd fsm # Constrain all select calls below inside the top module`
Add smoke tests to tests/xilinx 2019-09-10 00:08:03 -05:00
			`select -assert-count 1 t:BUFG`
xilinx: Improve flip-flop handling. This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. 2019-11-20 23:30:06 -06:00			`select -assert-count 4 t:FDRE`
			`select -assert-count 1 t:FDSE`
			`select -assert-count 1 t:LUT2`
xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 06:42:26 -06:00			`select -assert-count 3 t:LUT5`
			`select -assert-count 1 t:LUT6`
Fix xilinx tests, when iopads are default 2019-12-21 06:18:44 -06:00			`select -assert-none t:BUFG t:IBUF t:OBUF t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D`