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12 lines
197 B
Verilog
12 lines
197 B
Verilog
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(* abc9_flop, lib_whitebox *)
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module $__PP3_DFFEPC_SYNCONLY (
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output Q,
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input D,
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input CLK,
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input EN,
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);
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dffepc ff (.Q(Q), .D(D), .CLK(CLK), .EN(EN), .PRE(1'b0), .CLR(1'b0));
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endmodule
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