mirror of https://github.com/YosysHQ/yosys.git
32 lines
575 B
Plaintext
32 lines
575 B
Plaintext
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read_verilog <<EOF
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module top();
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wire a, b, c;
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endmodule
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EOF
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proc
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hierarchy -top top
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rename -seed 2 -scramble-name w:*
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select -assert-none w:a w:b w:c
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select -assert-count 3 w:$_*_
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select -assert-none w:$_*_ %% %n
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design -reset
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read_verilog <<EOF
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module foo(input a, b, output c);
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assign c = a + b;
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endmodule
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module top();
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wire a, b, c;
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foo bar(.a(a), .b(b), .c(c));
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endmodule
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EOF
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proc
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hierarchy -top top
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rename -seed 2 -scramble-name c:bar
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select -assert-none c:bar
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select -assert-count 1 c:$_*_
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select -assert-none c:$_*_ w:* foo/c:$add$<<EOF:2$1 %% %n
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