mirror of https://github.com/YosysHQ/yosys.git
26 lines
455 B
Plaintext
26 lines
455 B
Plaintext
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read_verilog -formal <<EOT
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module top(input a, b, c, d);
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always @* begin
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if (a) assert (b == c);
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if (!a) assert (b != c);
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if (b) assume (c);
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if (c) cover (d);
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end
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endmodule
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EOT
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prep -top top
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select -assert-count 1 t:$cover
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chformal -cover -coverenable
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select -assert-count 2 t:$cover
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chformal -assert -coverenable
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select -assert-count 4 t:$cover
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chformal -assume -coverenable
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select -assert-count 5 t:$cover
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