mirror of https://github.com/YosysHQ/yosys.git
15 lines
185 B
Verilog
15 lines
185 B
Verilog
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// D flip-flop Code
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module d_ff ( d, clk, q, q_bar);
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input d ,clk;
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output q, q_bar;
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wire d ,clk;
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reg q, q_bar;
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always @ (posedge clk)
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begin
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q <= d;
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q_bar <= !d;
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end
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endmodule
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