2021-09-24 14:50:26 -05:00
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read_verilog -D NO_INIT ../common/dffs.v
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2021-09-13 10:16:15 -05:00
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design -save read
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hierarchy -top dff
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proc
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equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_BUFG
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select -assert-count 1 t:CC_DFF
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select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
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design -load read
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hierarchy -top dffe
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proc
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equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_BUFG
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select -assert-count 1 t:CC_DFF
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select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
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