2019-12-31 20:29:29 -06:00
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# NB: Box inputs/outputs must each be in the same order
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# as their corresponding module definition
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# (with exceptions detailed below)
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2019-06-22 16:33:47 -05:00
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2019-06-14 06:02:12 -05:00
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# Box 1 : CCU2C (2xCARRY + 2xLUT4)
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2019-12-31 20:29:29 -06:00
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# (Exception: carry chain input/output must be the
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# last input and output and the entire bus has been
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# moved there overriding the otherwise
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2019-06-26 22:00:15 -05:00
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# alphabetical ordering)
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2019-06-14 06:02:12 -05:00
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# name ID w/b ins outs
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CCU2C 1 1 9 3
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2019-12-31 20:29:29 -06:00
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#A0 B0 C0 D0 A1 B1 C1 D1 CIN
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379 379 275 141 - - - - 257 # S0
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630 630 526 392 379 379 275 141 273 # S1
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516 516 412 278 516 516 412 278 43 # COUT
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2019-06-14 06:02:12 -05:00
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2019-08-20 20:59:03 -05:00
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# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
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# name ID w/b ins outs
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2019-10-04 13:04:10 -05:00
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$__ABC9_DPR16X4_COMB 2 0 8 4
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2019-12-31 20:42:11 -06:00
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#$DO0 $DO1 $DO2 $DO3 RAD0 RAD1 RAD2 RAD3
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2019-12-31 20:29:29 -06:00
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0 0 0 0 141 379 275 379 # DO0
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0 0 0 0 141 379 275 379 # DO1
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0 0 0 0 141 379 275 379 # DO2
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0 0 0 0 141 379 275 379 # DO3
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2019-06-14 06:02:12 -05:00
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# Box 3 : PFUMX (MUX2)
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# name ID w/b ins outs
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PFUMX 3 1 3 1
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#ALUT BLUT C0
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2019-12-31 20:29:29 -06:00
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98 98 151 # Z
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2019-06-14 06:02:12 -05:00
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# Box 4 : L6MUX21 (MUX2)
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# name ID w/b ins outs
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L6MUX21 4 1 3 1
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#D0 D1 SD
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2019-12-31 20:29:29 -06:00
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140 141 148 # Z
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