yosys/manual/FILES_Prog/test.v

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2013-07-20 08:19:12 -05:00
module uut(in1, in2, in3, out1, out2);
input [8:0] in1, in2, in3;
output [8:0] out1, out2;
assign out1 = in1 + in2 + (in3 >> 4);
endmodule