mirror of https://github.com/YosysHQ/yosys.git
43 lines
956 B
Plaintext
43 lines
956 B
Plaintext
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read_verilog muxpack.v
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design -save read
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hierarchy -top mux_if_unbal_4_1
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prep
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design -save gold
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muxpack
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opt
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stat
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select -assert-count 1 t:$pmux
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top mux_if_unbal_5_3
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prep
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design -save gold
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muxpack
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opt
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stat
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select -assert-count 1 t:$pmux
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top mux_if_unbal_5_3_invert
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prep
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design -save gold
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muxpack
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opt
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stat
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select -assert-count 1 t:$pmux
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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