yosys/techlibs/xilinx/cells.lut

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2019-04-09 16:33:37 -05:00
# Max delays from https://pastebin.com/v2hrcksd
# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
# Since LUT delays are pushed onto the fabric as routing delays,
# assume each input costs +100ps
# K area delay
1 11 224
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6 20 224 324 424 524 624 724
7 40 224 324 424 524 624 724 1020
8 80 224 324 424 524 624 724 1020 1293