mirror of https://github.com/YosysHQ/yosys.git
28 lines
807 B
Verilog
28 lines
807 B
Verilog
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module axis_test(aclk, tready);
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input aclk, tready;
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wire aresetn, tvalid;
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wire [7:0] tdata;
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integer counter = 0;
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reg aresetn = 0;
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axis_master uut (aclk, aresetn, tvalid, tready, tdata);
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always @(posedge aclk) begin
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if (aresetn && tready && tvalid) begin
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if (counter == 0) assert(tdata == 19);
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if (counter == 1) assert(tdata == 99);
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if (counter == 2) assert(tdata == 1);
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if (counter == 3) assert(tdata == 244);
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if (counter == 4) assert(tdata == 133);
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if (counter == 5) assert(tdata == 209);
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if (counter == 6) assert(tdata == 241);
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if (counter == 7) assert(tdata == 137);
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if (counter == 8) assert(tdata == 176);
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if (counter == 9) assert(tdata == 6);
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counter <= counter + 1;
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end
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aresetn <= 1;
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end
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endmodule
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