mirror of https://github.com/YosysHQ/yosys.git
855 lines
23 KiB
Python
855 lines
23 KiB
Python
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#!/usr/bin/env python3
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# Based on Xilinx cells_xtra.py; modified for Lattice's structure
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from argparse import ArgumentParser
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from io import StringIO
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from enum import Enum, auto
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import os.path
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import sys
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import re
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class Cell:
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def __init__(self, name, keep=False, port_attrs={}):
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self.name = name
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self.keep = keep
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self.port_attrs = port_attrs
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self.found = False
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class State(Enum):
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OUTSIDE = auto()
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IN_MODULE = auto()
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IN_OTHER_MODULE = auto()
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IN_FUNCTION = auto()
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IN_TASK = auto()
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devices = [
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("cells_bb_ecp5.v", "ecp5u", [
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#Cell("AND2"),
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#Cell("AND3"),
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#Cell("AND4"),
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#Cell("AND5"),
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#Cell("BB"),
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#Cell("BBPD"),
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#Cell("BBPU"),
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#Cell("CCU2C"),
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#Cell("FD1P3AX"),
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#Cell("FD1P3AY"),
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#Cell("FD1P3BX"),
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#Cell("FD1P3DX"),
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#Cell("FD1P3IX"),
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#Cell("FD1P3JX"),
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#Cell("FD1S3AX"),
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#Cell("FD1S3AY"),
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#Cell("FD1S3BX"),
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#Cell("FD1S3DX"),
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#Cell("FD1S3IX"),
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#Cell("FD1S3JX"),
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#Cell("FL1P3AY"),
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#Cell("FL1P3AZ"),
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#Cell("FL1P3BX"),
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#Cell("FL1P3DX"),
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#Cell("FL1P3IY"),
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#Cell("FL1P3JY"),
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#Cell("FL1S3AX"),
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#Cell("FL1S3AY"),
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Cell("GSR", True),
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#Cell("IB"),
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#Cell("IBPD"),
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#Cell("IBPU"),
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#Cell("IFS1P3BX"),
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#Cell("IFS1P3DX"),
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#Cell("IFS1P3IX"),
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#Cell("IFS1P3JX"),
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#Cell("IFS1S1B"),
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#Cell("IFS1S1D"),
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#Cell("IFS1S1I"),
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#Cell("IFS1S1J"),
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#Cell("ILVDS"),
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#Cell("INV"),
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#Cell("L6MUX21"),
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#Cell("LUT4"),
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#Cell("LUT5"),
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#Cell("LUT6"),
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#Cell("LUT7"),
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#Cell("LUT8"),
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#Cell("MUX161"),
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#Cell("MUX21"),
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#Cell("MUX321"),
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#Cell("MUX41"),
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#Cell("MUX81"),
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#Cell("ND2"),
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#Cell("ND3"),
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#Cell("ND4"),
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#Cell("ND5"),
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#Cell("NR2"),
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#Cell("NR3"),
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#Cell("NR4"),
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#Cell("NR5"),
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#Cell("OB"),
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#Cell("OBCO"),
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#Cell("OBZ"),
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#Cell("OBZPU"),
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#Cell("OFS1P3BX"),
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#Cell("OFS1P3DX"),
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#Cell("OFS1P3IX"),
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#Cell("OFS1P3JX"),
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#Cell("OLVDS"),
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#Cell("OR2"),
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#Cell("OR3"),
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#Cell("OR4"),
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#Cell("OR5"),
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#Cell("PFUMX"),
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Cell("PUR"),
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#Cell("ROM128X1A"),
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#Cell("ROM16X1A"),
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#Cell("ROM256X1A"),
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#Cell("ROM32X1A"),
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#Cell("ROM64X1A"),
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Cell("SGSR", True),
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#Cell("VHI"),
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#Cell("VLO"),
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#Cell("XNOR2"),
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#Cell("XNOR3"),
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#Cell("XNOR4"),
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#Cell("XNOR5"),
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#Cell("XOR11"),
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#Cell("XOR2"),
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#Cell("XOR21"),
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#Cell("XOR3"),
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#Cell("XOR4"),
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#Cell("XOR5"),
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Cell("DP16KD"),
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Cell("PDPW16KD"),
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#Cell("DPR16X4C"),
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#Cell("SPR16X4C"),
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#Cell("LVDSOB"),
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#Cell("IMIPI"),
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#Cell("MULT9X9C"),
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#Cell("MULT9X9D"),
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#Cell("MULT18X18C"),
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Cell("MULT18X18D"),
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#Cell("ALU24A"),
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#Cell("ALU54A"),
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#Cell("ALU24B"),
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Cell("ALU54B"),
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#Cell("PRADD9A"),
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#Cell("PRADD18A"),
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#Cell("BCINRD"),
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#Cell("BCLVDSOB"),
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#Cell("INRDB"),
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Cell("CLKDIVF"),
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Cell("PCSCLKDIV"),
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Cell("DCSC"),
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Cell("DCCA"),
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Cell("ECLKSYNCB"),
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Cell("ECLKBRIDGECS"),
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#Cell("PLLREFCS"),
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Cell("DELAYF"),
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Cell("DELAYG"),
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#Cell("START"),
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Cell("USRMCLK", True),
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Cell("DQSBUFM"),
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Cell("DDRDLLA"),
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Cell("DLLDELD"),
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Cell("IDDRX1F"),
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Cell("IDDRX2F"),
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Cell("IDDR71B"),
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Cell("IDDRX2DQA"),
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Cell("ODDRX1F"),
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Cell("ODDRX2F"),
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Cell("ODDR71B"),
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Cell("OSHX2A"),
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Cell("TSHX2DQA"),
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Cell("TSHX2DQSA"),
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Cell("ODDRX2DQA"),
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Cell("ODDRX2DQSB"),
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Cell("EHXPLLL"),
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Cell("DTR"),
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Cell("OSCG"),
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Cell("EXTREFB"),
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Cell("JTAGG", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
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#Cell("SEDGA"),
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Cell("DCUA", True, port_attrs={'CH0_HDINP': ['iopad_external_pin'], 'CH1_HDINP': ['iopad_external_pin'], 'CH0_HDINN': ['iopad_external_pin'], 'CH1_HDINN': ['iopad_external_pin']}),
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]),
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("cells_bb_xo2.v", "machxo2", [
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#Cell("AGEB2"),
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#Cell("ALEB2"),
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#Cell("AND2"),
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#Cell("AND3"),
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#Cell("AND4"),
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#Cell("AND5"),
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#Cell("ANEB2"),
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#Cell("BB"),
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#Cell("BBPD"),
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#Cell("BBPU"),
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#Cell("BBW"),
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#Cell("CB2"),
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#Cell("CD2"),
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#Cell("CU2"),
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#Cell("FADD2B"),
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#Cell("FADSU2"),
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#Cell("FD1P3AX"),
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#Cell("FD1P3AY"),
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#Cell("FD1P3BX"),
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#Cell("FD1P3DX"),
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#Cell("FD1P3IX"),
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#Cell("FD1P3JX"),
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#Cell("FD1S1A"),
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#Cell("FD1S1AY"),
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#Cell("FD1S1B"),
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#Cell("FD1S1D"),
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#Cell("FD1S1I"),
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#Cell("FD1S1J"),
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#Cell("FD1S3AX"),
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#Cell("FD1S3AY"),
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#Cell("FD1S3BX"),
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#Cell("FD1S3DX"),
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#Cell("FD1S3IX"),
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#Cell("FD1S3JX"),
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#Cell("FL1P3AY"),
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#Cell("FL1P3AZ"),
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#Cell("FL1P3BX"),
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#Cell("FL1P3DX"),
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#Cell("FL1P3IY"),
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#Cell("FL1P3JY"),
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#Cell("FL1S1A"),
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#Cell("FL1S1AY"),
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#Cell("FL1S1B"),
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#Cell("FL1S1D"),
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#Cell("FL1S1I"),
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#Cell("FL1S1J"),
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#Cell("FL1S3AX"),
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#Cell("FL1S3AY"),
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#Cell("FSUB2B"),
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Cell("GSR", True),
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#Cell("IB"),
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#Cell("IBPD"),
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#Cell("IBPU"),
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#Cell("IFS1P3BX"),
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#Cell("IFS1P3DX"),
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#Cell("IFS1P3IX"),
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#Cell("IFS1P3JX"),
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#Cell("ILVDS"),
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#Cell("INV"),
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#Cell("L6MUX21"),
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#Cell("LB2P3AX"),
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#Cell("LB2P3AY"),
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#Cell("LB2P3BX"),
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#Cell("LB2P3DX"),
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#Cell("LB2P3IX"),
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#Cell("LB2P3JX"),
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#Cell("LD2P3AX"),
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#Cell("LD2P3AY"),
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#Cell("LD2P3BX"),
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#Cell("LD2P3DX"),
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#Cell("LD2P3IX"),
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#Cell("LD2P3JX"),
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#Cell("LU2P3AX"),
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#Cell("LU2P3AY"),
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#Cell("LU2P3BX"),
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#Cell("LU2P3DX"),
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#Cell("LU2P3IX"),
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#Cell("LU2P3JX"),
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#Cell("MULT2"),
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#Cell("MUX161"),
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#Cell("MUX21"),
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#Cell("MUX321"),
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#Cell("MUX41"),
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#Cell("MUX81"),
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#Cell("ND2"),
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#Cell("ND3"),
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#Cell("ND4"),
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#Cell("ND5"),
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#Cell("NR2"),
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#Cell("NR3"),
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#Cell("NR4"),
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#Cell("NR5"),
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#Cell("OB"),
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#Cell("OBCO"),
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#Cell("OBZ"),
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#Cell("OBZPU"),
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#Cell("OFS1P3BX"),
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#Cell("OFS1P3DX"),
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#Cell("OFS1P3IX"),
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#Cell("OFS1P3JX"),
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#Cell("OLVDS"),
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#Cell("OR2"),
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#Cell("OR3"),
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#Cell("OR4"),
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#Cell("OR5"),
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#Cell("LUT4"),
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#Cell("LUT5"),
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#Cell("LUT6"),
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#Cell("LUT7"),
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#Cell("LUT8"),
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#Cell("PFUMX"),
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#Cell("PUR"),
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#Cell("ROM128X1A"),
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#Cell("ROM16X1A"),
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#Cell("ROM256X1A"),
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#Cell("ROM32X1A"),
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#Cell("ROM64X1A"),
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#Cell("CCU2D"),
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#Cell("VHI"),
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#Cell("VLO"),
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#Cell("XNOR2"),
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#Cell("XNOR3"),
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#Cell("XNOR4"),
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#Cell("XNOR5"),
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#Cell("XOR11"),
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#Cell("XOR2"),
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#Cell("XOR21"),
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#Cell("XOR3"),
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#Cell("XOR4"),
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#Cell("XOR5"),
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#Cell("IFS1S1B"),
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#Cell("IFS1S1D"),
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#Cell("IFS1S1I"),
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#Cell("IFS1S1J"),
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#Cell("DPR16X4C"),
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#Cell("SPR16X4C"),
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Cell("SGSR", True),
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Cell("DP8KC"),
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Cell("PDPW8KC"),
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Cell("SP8KC"),
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Cell("FIFO8KB"),
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#Cell("CLKDIVC"),
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Cell("DCMA"),
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#Cell("ECLKSYNCA"),
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#Cell("ECLKBRIDGECS"),
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Cell("DCCA"),
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#Cell("JTAGF"),
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#Cell("START"),
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#Cell("SEDFA"),
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#Cell("SEDFB"),
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#Cell("IDDRXE"),
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#Cell("IDDRX2E"),
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#Cell("IDDRX4B"),
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#Cell("IDDRDQSX1A"),
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#Cell("IDDRX71A"),
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#Cell("ODDRXE"),
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#Cell("ODDRX2E"),
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#Cell("ODDRX4B"),
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#Cell("ODDRDQSX1A"),
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#Cell("ODDRX71A"),
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#Cell("TDDRA"),
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#Cell("DQSBUFH"),
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#Cell("DQSDLLC"),
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#Cell("DELAYE"),
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#Cell("DELAYD"),
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#Cell("DLLDELC"),
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#Cell("CLKFBBUFA"),
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#Cell("PCNTR"),
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#Cell("BCINRD"),
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#Cell("BCLVDSO"),
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#Cell("INRDB"),
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#Cell("LVDSOB"),
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#Cell("PG"),
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Cell("EHXPLLJ"),
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#Cell("PLLREFCS"),
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Cell("OSCH"),
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#Cell("EFB"),
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#Cell("TSALL"),
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]),
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("cells_bb_xo3.v", "machxo3lf", [
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#Cell("AGEB2"),
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#Cell("ALEB2"),
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#Cell("AND2"),
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#Cell("AND3"),
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#Cell("AND4"),
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#Cell("AND5"),
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#Cell("ANEB2"),
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#Cell("BB"),
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#Cell("BBPD"),
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#Cell("BBPU"),
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#Cell("BBW"),
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#Cell("CB2"),
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#Cell("CD2"),
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#Cell("CU2"),
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#Cell("FADD2B"),
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#Cell("FADSU2"),
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#Cell("FD1P3AX"),
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#Cell("FD1P3AY"),
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#Cell("FD1P3BX"),
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#Cell("FD1P3DX"),
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#Cell("FD1P3IX"),
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#Cell("FD1P3JX"),
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#Cell("FD1S1A"),
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#Cell("FD1S1AY"),
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#Cell("FD1S1B"),
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#Cell("FD1S1D"),
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#Cell("FD1S1I"),
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#Cell("FD1S1J"),
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#Cell("FD1S3AX"),
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#Cell("FD1S3AY"),
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#Cell("FD1S3BX"),
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#Cell("FD1S3DX"),
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#Cell("FD1S3IX"),
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#Cell("FD1S3JX"),
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#Cell("FL1P3AY"),
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#Cell("FL1P3AZ"),
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#Cell("FL1P3BX"),
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#Cell("FL1P3DX"),
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#Cell("FL1P3IY"),
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#Cell("FL1P3JY"),
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#Cell("FL1S1A"),
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#Cell("FL1S1AY"),
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#Cell("FL1S1B"),
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#Cell("FL1S1D"),
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#Cell("FL1S1I"),
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#Cell("FL1S1J"),
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#Cell("FL1S3AX"),
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#Cell("FL1S3AY"),
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#Cell("FSUB2B"),
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Cell("GSR", True),
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#Cell("IB"),
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#Cell("IBPD"),
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#Cell("IBPU"),
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#Cell("IFS1P3BX"),
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#Cell("IFS1P3DX"),
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#Cell("IFS1P3IX"),
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#Cell("IFS1P3JX"),
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#Cell("ILVDS"),
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#Cell("INV"),
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#Cell("L6MUX21"),
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#Cell("LB2P3AX"),
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#Cell("LB2P3AY"),
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#Cell("LB2P3BX"),
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#Cell("LB2P3DX"),
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#Cell("LB2P3IX"),
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#Cell("LB2P3JX"),
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#Cell("LD2P3AX"),
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#Cell("LD2P3AY"),
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#Cell("LD2P3BX"),
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#Cell("LD2P3DX"),
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#Cell("LD2P3IX"),
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#Cell("LD2P3JX"),
|
||
|
#Cell("LU2P3AX"),
|
||
|
#Cell("LU2P3AY"),
|
||
|
#Cell("LU2P3BX"),
|
||
|
#Cell("LU2P3DX"),
|
||
|
#Cell("LU2P3IX"),
|
||
|
#Cell("LU2P3JX"),
|
||
|
#Cell("MULT2"),
|
||
|
#Cell("MUX161"),
|
||
|
#Cell("MUX21"),
|
||
|
#Cell("MUX321"),
|
||
|
#Cell("MUX41"),
|
||
|
#Cell("MUX81"),
|
||
|
#Cell("ND2"),
|
||
|
#Cell("ND3"),
|
||
|
#Cell("ND4"),
|
||
|
#Cell("ND5"),
|
||
|
#Cell("NR2"),
|
||
|
#Cell("NR3"),
|
||
|
#Cell("NR4"),
|
||
|
#Cell("NR5"),
|
||
|
#Cell("OB"),
|
||
|
#Cell("OBCO"),
|
||
|
#Cell("OBZ"),
|
||
|
#Cell("OBZPU"),
|
||
|
#Cell("OFS1P3BX"),
|
||
|
#Cell("OFS1P3DX"),
|
||
|
#Cell("OFS1P3IX"),
|
||
|
#Cell("OFS1P3JX"),
|
||
|
#Cell("OLVDS"),
|
||
|
#Cell("OR2"),
|
||
|
#Cell("OR3"),
|
||
|
#Cell("OR4"),
|
||
|
#Cell("OR5"),
|
||
|
#Cell("LUT4"),
|
||
|
#Cell("LUT5"),
|
||
|
#Cell("LUT6"),
|
||
|
#Cell("LUT7"),
|
||
|
#Cell("LUT8"),
|
||
|
#Cell("PFUMX"),
|
||
|
#Cell("PUR"),
|
||
|
#Cell("ROM128X1A"),
|
||
|
#Cell("ROM16X1A"),
|
||
|
#Cell("ROM256X1A"),
|
||
|
#Cell("ROM32X1A"),
|
||
|
#Cell("ROM64X1A"),
|
||
|
#Cell("CCU2D"),
|
||
|
#Cell("VHI"),
|
||
|
#Cell("VLO"),
|
||
|
#Cell("XNOR2"),
|
||
|
#Cell("XNOR3"),
|
||
|
#Cell("XNOR4"),
|
||
|
#Cell("XNOR5"),
|
||
|
#Cell("XOR11"),
|
||
|
#Cell("XOR2"),
|
||
|
#Cell("XOR21"),
|
||
|
#Cell("XOR3"),
|
||
|
#Cell("XOR4"),
|
||
|
#Cell("XOR5"),
|
||
|
#Cell("IFS1S1B"),
|
||
|
#Cell("IFS1S1D"),
|
||
|
#Cell("IFS1S1I"),
|
||
|
#Cell("IFS1S1J"),
|
||
|
#Cell("DPR16X4C"),
|
||
|
#Cell("SPR16X4C"),
|
||
|
Cell("SGSR", True),
|
||
|
Cell("DP8KC"),
|
||
|
Cell("PDPW8KC"),
|
||
|
Cell("SP8KC"),
|
||
|
Cell("FIFO8KB"),
|
||
|
#Cell("CLKDIVC"),
|
||
|
Cell("DCMA"),
|
||
|
#Cell("ECLKSYNCA"),
|
||
|
#Cell("ECLKBRIDGECS"),
|
||
|
Cell("DCCA"),
|
||
|
#Cell("JTAGF"),
|
||
|
#Cell("START"),
|
||
|
#Cell("SEDFA"),
|
||
|
#Cell("SEDFB"),
|
||
|
#Cell("IDDRXE"),
|
||
|
#Cell("IDDRX2E"),
|
||
|
#Cell("IDDRX4B"),
|
||
|
#Cell("IDDRX71A"),
|
||
|
#Cell("ODDRXE"),
|
||
|
#Cell("ODDRX2E"),
|
||
|
#Cell("ODDRX4B"),
|
||
|
#Cell("ODDRX71A"),
|
||
|
#Cell("DQSDLLC"),
|
||
|
#Cell("DELAYE"),
|
||
|
#Cell("DELAYD"),
|
||
|
#Cell("DLLDELC"),
|
||
|
#Cell("CLKFBBUFA"),
|
||
|
#Cell("PCNTR"),
|
||
|
#Cell("BCINRD"),
|
||
|
#Cell("BCLVDSO"),
|
||
|
#Cell("INRDB"),
|
||
|
#Cell("LVDSOB"),
|
||
|
#Cell("PG"),
|
||
|
Cell("EHXPLLJ"),
|
||
|
#Cell("PLLREFCS"),
|
||
|
Cell("OSCH"),
|
||
|
#Cell("EFB"),
|
||
|
#Cell("TSALL"),
|
||
|
]),
|
||
|
("cells_bb_xo3d.v", "machxo3d", [
|
||
|
#Cell("AGEB2"),
|
||
|
#Cell("ALEB2"),
|
||
|
#Cell("AND2"),
|
||
|
#Cell("AND3"),
|
||
|
#Cell("AND4"),
|
||
|
#Cell("AND5"),
|
||
|
#Cell("ANEB2"),
|
||
|
#Cell("BB"),
|
||
|
#Cell("BBPD"),
|
||
|
#Cell("BBPU"),
|
||
|
#Cell("BBI3C"),
|
||
|
#Cell("BBW"),
|
||
|
#Cell("CB2"),
|
||
|
#Cell("CD2"),
|
||
|
#Cell("CU2"),
|
||
|
#Cell("FADD2B"),
|
||
|
#Cell("FADSU2"),
|
||
|
#Cell("FD1P3AX"),
|
||
|
#Cell("FD1P3AY"),
|
||
|
#Cell("FD1P3BX"),
|
||
|
#Cell("FD1P3DX"),
|
||
|
#Cell("FD1P3IX"),
|
||
|
#Cell("FD1P3JX"),
|
||
|
#Cell("FD1S1A"),
|
||
|
#Cell("FD1S1AY"),
|
||
|
#Cell("FD1S1B"),
|
||
|
#Cell("FD1S1D"),
|
||
|
#Cell("FD1S1I"),
|
||
|
#Cell("FD1S1J"),
|
||
|
#Cell("FD1S3AX"),
|
||
|
#Cell("FD1S3AY"),
|
||
|
#Cell("FD1S3BX"),
|
||
|
#Cell("FD1S3DX"),
|
||
|
#Cell("FD1S3IX"),
|
||
|
#Cell("FD1S3JX"),
|
||
|
#Cell("FL1P3AY"),
|
||
|
#Cell("FL1P3AZ"),
|
||
|
#Cell("FL1P3BX"),
|
||
|
#Cell("FL1P3DX"),
|
||
|
#Cell("FL1P3IY"),
|
||
|
#Cell("FL1P3JY"),
|
||
|
#Cell("FL1S1A"),
|
||
|
#Cell("FL1S1AY"),
|
||
|
#Cell("FL1S1B"),
|
||
|
#Cell("FL1S1D"),
|
||
|
#Cell("FL1S1I"),
|
||
|
#Cell("FL1S1J"),
|
||
|
#Cell("FL1S3AX"),
|
||
|
#Cell("FL1S3AY"),
|
||
|
#Cell("FSUB2B"),
|
||
|
Cell("GSR", True),
|
||
|
#Cell("IB"),
|
||
|
#Cell("IBPD"),
|
||
|
#Cell("IBPU"),
|
||
|
#Cell("IFS1P3BX"),
|
||
|
#Cell("IFS1P3DX"),
|
||
|
#Cell("IFS1P3IX"),
|
||
|
#Cell("IFS1P3JX"),
|
||
|
#Cell("ILVDS"),
|
||
|
#Cell("INV"),
|
||
|
#Cell("L6MUX21"),
|
||
|
#Cell("LB2P3AX"),
|
||
|
#Cell("LB2P3AY"),
|
||
|
#Cell("LB2P3BX"),
|
||
|
#Cell("LB2P3DX"),
|
||
|
#Cell("LB2P3IX"),
|
||
|
#Cell("LB2P3JX"),
|
||
|
#Cell("LD2P3AX"),
|
||
|
#Cell("LD2P3AY"),
|
||
|
#Cell("LD2P3BX"),
|
||
|
#Cell("LD2P3DX"),
|
||
|
#Cell("LD2P3IX"),
|
||
|
#Cell("LD2P3JX"),
|
||
|
#Cell("LU2P3AX"),
|
||
|
#Cell("LU2P3AY"),
|
||
|
#Cell("LU2P3BX"),
|
||
|
#Cell("LU2P3DX"),
|
||
|
#Cell("LU2P3IX"),
|
||
|
#Cell("LU2P3JX"),
|
||
|
#Cell("MULT2"),
|
||
|
#Cell("MUX161"),
|
||
|
#Cell("MUX21"),
|
||
|
#Cell("MUX321"),
|
||
|
#Cell("MUX41"),
|
||
|
#Cell("MUX81"),
|
||
|
#Cell("ND2"),
|
||
|
#Cell("ND3"),
|
||
|
#Cell("ND4"),
|
||
|
#Cell("ND5"),
|
||
|
#Cell("NR2"),
|
||
|
#Cell("NR3"),
|
||
|
#Cell("NR4"),
|
||
|
#Cell("NR5"),
|
||
|
#Cell("OB"),
|
||
|
#Cell("OBCO"),
|
||
|
#Cell("OBZ"),
|
||
|
#Cell("OBZPU"),
|
||
|
#Cell("OFS1P3BX"),
|
||
|
#Cell("OFS1P3DX"),
|
||
|
#Cell("OFS1P3IX"),
|
||
|
#Cell("OFS1P3JX"),
|
||
|
#Cell("OLVDS"),
|
||
|
#Cell("OR2"),
|
||
|
#Cell("OR3"),
|
||
|
#Cell("OR4"),
|
||
|
#Cell("OR5"),
|
||
|
#Cell("LUT4"),
|
||
|
#Cell("LUT5"),
|
||
|
#Cell("LUT6"),
|
||
|
#Cell("LUT7"),
|
||
|
#Cell("LUT8"),
|
||
|
#Cell("PFUMX"),
|
||
|
#Cell("PUR"),
|
||
|
#Cell("ROM128X1A"),
|
||
|
#Cell("ROM16X1A"),
|
||
|
#Cell("ROM256X1A"),
|
||
|
#Cell("ROM32X1A"),
|
||
|
#Cell("ROM64X1A"),
|
||
|
#Cell("CCU2D"),
|
||
|
#Cell("VHI"),
|
||
|
#Cell("VLO"),
|
||
|
#Cell("XNOR2"),
|
||
|
#Cell("XNOR3"),
|
||
|
#Cell("XNOR4"),
|
||
|
#Cell("XNOR5"),
|
||
|
#Cell("XOR11"),
|
||
|
#Cell("XOR2"),
|
||
|
#Cell("XOR21"),
|
||
|
#Cell("XOR3"),
|
||
|
#Cell("XOR4"),
|
||
|
#Cell("XOR5"),
|
||
|
#Cell("IFS1S1B"),
|
||
|
#Cell("IFS1S1D"),
|
||
|
#Cell("IFS1S1I"),
|
||
|
#Cell("IFS1S1J"),
|
||
|
#Cell("DPR16X4C"),
|
||
|
#Cell("SPR16X4C"),
|
||
|
Cell("SGSR", True),
|
||
|
Cell("DP8KC"),
|
||
|
Cell("PDPW8KC"),
|
||
|
Cell("SP8KC"),
|
||
|
Cell("FIFO8KB"),
|
||
|
#Cell("CLKDIVC"),
|
||
|
Cell("DCMA"),
|
||
|
#Cell("ECLKSYNCA"),
|
||
|
#Cell("ECLKBRIDGECS"),
|
||
|
Cell("DCCA"),
|
||
|
#Cell("JTAGF"),
|
||
|
#Cell("START"),
|
||
|
#Cell("SEDFA"),
|
||
|
#Cell("SEDFB"),
|
||
|
#Cell("IDDRXE"),
|
||
|
#Cell("IDDRX2E"),
|
||
|
#Cell("IDDRX4B"),
|
||
|
#Cell("IDDRX71A"),
|
||
|
#Cell("ODDRXE"),
|
||
|
#Cell("ODDRX2E"),
|
||
|
#Cell("ODDRX4B"),
|
||
|
#Cell("ODDRX71A"),
|
||
|
#Cell("DQSDLLC"),
|
||
|
#Cell("DELAYE"),
|
||
|
#Cell("DELAYD"),
|
||
|
#Cell("DLLDELC"),
|
||
|
#Cell("CLKFBBUFA"),
|
||
|
#Cell("PCNTR"),
|
||
|
#Cell("BCINRD"),
|
||
|
#Cell("BCLVDSO"),
|
||
|
#Cell("INRDB"),
|
||
|
#Cell("LVDSOB"),
|
||
|
#Cell("PG"),
|
||
|
Cell("EHXPLLJ"),
|
||
|
#Cell("PLLREFCS"),
|
||
|
Cell("OSCJ"),
|
||
|
#Cell("EFBB"),
|
||
|
#Cell("TSALL"),
|
||
|
#Cell("ESBA"),
|
||
|
#Cell("BCSLEWRATEA"),
|
||
|
])
|
||
|
]
|
||
|
|
||
|
def xtract_cells_decl(device, cells, dirs, outf):
|
||
|
fname = os.path.join(dir, device + '.v')
|
||
|
with open(fname) as f:
|
||
|
state = State.OUTSIDE
|
||
|
# Probably the most horrible Verilog "parser" ever written.
|
||
|
cell = None
|
||
|
kind = None
|
||
|
for l in f:
|
||
|
l, _, comment = l.partition('//')
|
||
|
l = l.strip()
|
||
|
m = re.search(r'synthesis .*black_box_pad_pin="([^"]*)"', comment)
|
||
|
if m:
|
||
|
iopad_pin = set(m.group(1).split(","))
|
||
|
|
||
|
if l.startswith("module "):
|
||
|
cell_name = l[7:l.find('(')].strip()
|
||
|
cell = None
|
||
|
kind = None
|
||
|
module_ports = []
|
||
|
iopad_pin = set()
|
||
|
if state != State.OUTSIDE:
|
||
|
print('Nested modules in {}.'.format(fname))
|
||
|
sys.exit(1)
|
||
|
for c in cells:
|
||
|
if c.name != cell_name:
|
||
|
continue
|
||
|
cell = c
|
||
|
state = State.IN_MODULE
|
||
|
outf.write('(* blackbox *)')
|
||
|
if cell.keep:
|
||
|
outf.write(' (* keep *)\n')
|
||
|
else:
|
||
|
outf.write('\n')
|
||
|
outf.write('module {} (...);\n'.format(cell.name))
|
||
|
cell.found = True
|
||
|
if cell is None:
|
||
|
state = State.IN_OTHER_MODULE
|
||
|
elif l.startswith('task '):
|
||
|
if state == State.IN_MODULE:
|
||
|
state = State.IN_TASK
|
||
|
elif l.startswith('function '):
|
||
|
if state == State.IN_MODULE:
|
||
|
state = State.IN_FUNCTION
|
||
|
elif l == 'endtask':
|
||
|
if state == State.IN_TASK:
|
||
|
state = State.IN_MODULE
|
||
|
elif l == 'endfunction':
|
||
|
if state == State.IN_FUNCTION:
|
||
|
state = State.IN_MODULE
|
||
|
elif l == 'endmodule':
|
||
|
if state == State.IN_MODULE:
|
||
|
for kind, rng, port in module_ports:
|
||
|
for attr in cell.port_attrs.get(port, []):
|
||
|
outf.write(' (* {} *)\n'.format(attr))
|
||
|
if port in iopad_pin:
|
||
|
outf.write(' (* iopad_external_pin *)\n')
|
||
|
if rng is None:
|
||
|
outf.write(' {} {};\n'.format(kind, port))
|
||
|
else:
|
||
|
outf.write(' {} {} {};\n'.format(kind, rng, port))
|
||
|
outf.write(l + '\n')
|
||
|
outf.write('\n')
|
||
|
elif state != State.IN_OTHER_MODULE:
|
||
|
print('endmodule in weird place in {}.'.format(cell.name, fname))
|
||
|
sys.exit(1)
|
||
|
state = State.OUTSIDE
|
||
|
elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
|
||
|
l = l.strip()
|
||
|
if l == "":
|
||
|
continue
|
||
|
if l.endswith((';', ',', ")")):
|
||
|
l = l[:-1]
|
||
|
l = l.replace(")","")
|
||
|
if ';' in l:
|
||
|
print('Weird port line in {} [{}].'.format(fname, l))
|
||
|
sys.exit(1)
|
||
|
kind, _, ports = l.partition(' ')
|
||
|
for port in ports.split(','):
|
||
|
port = port.strip()
|
||
|
if port.startswith('['):
|
||
|
rng, port = port.split()
|
||
|
else:
|
||
|
rng = None
|
||
|
module_ports.append((kind, rng, port))
|
||
|
elif l.startswith('parameter ') and state == State.IN_MODULE:
|
||
|
l = l.strip()
|
||
|
if l.endswith((';', ',')):
|
||
|
l = l[:-1]
|
||
|
while ' ' in l:
|
||
|
l = l.replace(' ', ' ')
|
||
|
|
||
|
if "INITVAL" in l:
|
||
|
l = l.replace('"0x', "320'h")
|
||
|
l = l.replace('"', '')
|
||
|
if ';' in l:
|
||
|
print('Weird parameter line in {} [{}].'.format(fname, l))
|
||
|
sys.exit(1)
|
||
|
outf.write(' {};\n'.format(l))
|
||
|
elif kind is not None and state == State.IN_MODULE:
|
||
|
l = l.strip()
|
||
|
if l == "":
|
||
|
continue
|
||
|
if l.endswith((';', ',', ")")):
|
||
|
l = l[:-1]
|
||
|
l = l.replace(")","")
|
||
|
if ';' in l:
|
||
|
print('Weird port line in {} [{}].'.format(fname, l))
|
||
|
sys.exit(1)
|
||
|
ports = l
|
||
|
for port in ports.split(','):
|
||
|
port = port.strip()
|
||
|
if port.startswith('['):
|
||
|
rng, port = port.split()
|
||
|
else:
|
||
|
rng = None
|
||
|
module_ports.append((kind, rng, port))
|
||
|
|
||
|
if state != State.OUTSIDE:
|
||
|
print('endmodule not found in {}.'.format(fname))
|
||
|
sys.exit(1)
|
||
|
for cell in cells:
|
||
|
if not cell.found:
|
||
|
print('cell {} not found in {}.'.format(cell.name, fname))
|
||
|
if __name__ == '__main__':
|
||
|
parser = ArgumentParser(description='Extract Lattice blackbox cell definitions from Lattice Diamond.')
|
||
|
parser.add_argument('diamond_dir', nargs='?', default='/usr/local/diamond/3.12/')
|
||
|
args = parser.parse_args()
|
||
|
|
||
|
dirs = [
|
||
|
os.path.join(args.diamond_dir, 'cae_library/synthesis/verilog/'),
|
||
|
]
|
||
|
for dir in dirs:
|
||
|
if not os.path.isdir(dir):
|
||
|
print('{} is not a directory'.format(dir))
|
||
|
|
||
|
for fn, device, cells in devices:
|
||
|
out = StringIO()
|
||
|
xtract_cells_decl(device, cells, dirs, out)
|
||
|
with open(fn, 'w') as f:
|
||
|
f.write('// Created by cells_xtra.py from Lattice models\n')
|
||
|
f.write('\n')
|
||
|
f.write(out.getvalue())
|