mirror of https://github.com/YosysHQ/yosys.git
35 lines
1.1 KiB
Verilog
35 lines
1.1 KiB
Verilog
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`default_nettype none
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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(* force_downto *)
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
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NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
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.I1(1'b0), .I2(1'b0), .I3(1'b0), .I4(A[0]));
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end else
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if (WIDTH == 2) begin
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localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
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NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
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.I1(1'b0), .I2(1'b0), .I3(A[0]), .I4(A[1]));
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end else
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if (WIDTH == 3) begin
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localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
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NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
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.I1(1'b0), .I2(A[0]), .I3(A[1]), .I4(A[2]));
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end else
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if (WIDTH == 4) begin
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NX_LUT #(.lut_table(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(A[3]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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