mirror of https://github.com/YosysHQ/yosys.git
37 lines
629 B
Verilog
37 lines
629 B
Verilog
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module wandwor_test0 (A, B, C, D, X, Y, Z);
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input A, B, C, D;
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output wor X;
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output wand Y;
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output Z;
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assign X = A, X = B, Y = C, Y = D;
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foo foo_0 (C, D, X);
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foo foo_1 (A, B, Y);
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foo foo_2 (X, Y, Z);
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endmodule
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module wandwor_test1 (A, B, C, D, X, Y, Z);
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input [3:0] A, B, C, D;
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output wor [3:0] X;
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output wand [3:0] Y;
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output Z;
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bar bar_inst (
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.I0({A, B}),
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.I1({B, A}),
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.O({X, Y})
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);
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assign X = C, X = D;
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assign Y = C, Y = D;
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assign Z = ^{X,Y};
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endmodule
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module foo(input I0, I1, output O);
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assign O = I0 ^ I1;
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endmodule
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module bar(input [7:0] I0, I1, output [7:0] O);
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assign O = I0 + I1;
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endmodule
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