mirror of https://github.com/YosysHQ/yosys.git
12 lines
135 B
Verilog
12 lines
135 B
Verilog
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module top(
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input wire x,
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output reg y
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);
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always @* begin
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case (top.x)
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1: top.y = 0;
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0: top.y = 1;
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endcase
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end
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endmodule
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