mirror of https://github.com/YosysHQ/yosys.git
30 lines
923 B
Verilog
30 lines
923 B
Verilog
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`default_nettype none
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module Example(o1, o2);
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parameter [31:0] v1 = 10;
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parameter [31:0] v2 = 20;
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output [31:0] o1, o2;
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assign Example.o1 = Example.v1;
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assign Example.o2 = Example.v2;
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endmodule
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module ExampleLong(o1, o2);
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parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
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parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
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output [31:0] o1, o2;
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assign ExampleLong.o1 = ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
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assign ExampleLong.o2 = ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
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endmodule
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module top(
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output [31:0] a1, a2, b1, b2, c1, c2,
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output [31:0] d1, d2, e1, e2, f1, f2
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);
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Example a(a1, a2);
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Example #(1) b(b1, b2);
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Example #(1, 2) c(c1, c2);
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ExampleLong d(d1, d2);
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ExampleLong #(1) e(e1, e2);
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ExampleLong #(1, 2) f(f1, f2);
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endmodule
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