mirror of https://github.com/YosysHQ/yosys.git
30 lines
556 B
Systemverilog
30 lines
556 B
Systemverilog
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module top(
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output reg [7:0]
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out1, out2, out3, out4
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);
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initial begin
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begin : blk1
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reg x;
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x = 1;
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end
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out1 = blk1.x;
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begin : blk2
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reg x;
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x = 2;
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end : blk2
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out2 = blk2.x;
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end
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if (1) begin
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if (1) begin : blk3
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reg x;
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assign x = 3;
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end
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assign out3 = blk3.x;
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if (1) begin : blk4
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reg x;
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assign x = 4;
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end : blk4
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assign out4 = blk4.x;
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end
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endmodule
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