mirror of https://github.com/YosysHQ/yosys.git
22 lines
349 B
Verilog
22 lines
349 B
Verilog
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`default_nettype none
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module top(output wire x);
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generate
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if (1) begin : Z
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if (1) begin : A
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wire x;
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if (1) begin : B
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wire x;
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if (1) begin : C
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wire x;
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assign B.x = 0;
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wire z = A.B.C.x;
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end
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assign A.x = A.B.C.x;
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end
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assign B.C.x = B.x;
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end
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end
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endgenerate
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assign x = Z.A.x;
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endmodule
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